[PATCH] D126085: [RISCV] Add a subtarget feature to enable unaligned loads

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Is this meant to be "it works" or "it works without trapping for emulation"? Pretty much every EEI out there has misaligned accesses guaranteed to work, just not quickly, and in those cases you'd still want to avoid them as the inlined byte-wise code is far faster.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11810
   if (!VT.isVector())
-    return false;
+    return Subtarget.enableUnalignedMem();
 
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If returning true and Fast isn't null we should be setting it; some users pre-initialise it, but not all (I found one in GlobalISel and stopped looking)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D126085/new/

https://reviews.llvm.org/D126085