[PATCH] D125787: [RISCV] Fix RVV stack frame alignment bugs

Thu May 19 00:09:58 PDT 2022

frasercrmck added inline comments.

================
Comment at: llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll:55
 ; SPILL-O0-NEXT:    csrr a0, vlenb
+; SPILL-O0-NEXT:    slli a0, a0, 1
 ; SPILL-O0-NEXT:    sub sp, sp, a0
----------------
kito-cheng wrote:
> reames wrote:
> > Near as I can tell, these shifts are coming from the 16 byte minimum RVV alignment right?  Or is there some other cause I'm missing.
> > 
> > As noted in the top-level comment, I wonder if this is worthwhile.  
> Does it possible to re-align by this way?
> 
> ```
> csrr a0, vlenb
> addi a0, a0, 15
> andi a0, a0, -16
> sub sp, sp, a0
> ```
Technically I think we could, but because we may be in a situation where we only have sp/bp and we need to jump //over// the RVV section to reach callee saves or fixed objects, that would complicate the code we emit for frame offset calculations.

I think, on balance, having a "known" size for the RVV section is preferable, even if it may waste stack space on certain (zvl32b/zvl64b) configurations.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125787/new/

https://reviews.llvm.org/D125787