[PATCH] D125846: [StackProtector] Allow targets to specify an instruction is part of terminator sequence

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In D125846#3523981 <https://reviews.llvm.org/D125846#3523981>, @nemanjai wrote:

> In D125846#3523688 <https://reviews.llvm.org/D125846#3523688>, @arsenm wrote:
>
>> Why can't you just mark these instructions as being terminators? AMDGPU has to glue a lot of ALU instructions to terminators, and we just define terminator and nonterminator pseudo variants
>
> This seems like a less desirable path. Marking what is inherently a non-terminator instruction as a terminator seems likely to cause problems. I don't have a specific case in mind, but perhaps if some pass makes the assumption that it is safe to split a basic block into two that terminate with two terminators. It might be a safe thing to do except if some terminator is not actually a terminator.

Furthermore, this instruction is needed to set up the address for the call. The call itself is only a terminator because it is a tail call. Seems like we would have to have a rather complex set of conditions to decide whether to use a terminator variant or a non-terminator variant.


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https://reviews.llvm.org/D125846