[llvm] 25af3af - [NFC][AMDGPU][CodeGen] Use ArrayRef in TargetLowering functions
Shao-Ce SUN via llvm-commits
llvm-commits at lists.llvm.org
Tue May 17 19:50:40 PDT 2022
Author: Shao-Ce SUN
Date: 2022-05-18T10:50:23+08:00
New Revision: 25af3afa676191b2af328b6f03ee869d82a97f58
URL: https://github.com/llvm/llvm-project/commit/25af3afa676191b2af328b6f03ee869d82a97f58
DIFF: https://github.com/llvm/llvm-project/commit/25af3afa676191b2af328b6f03ee869d82a97f58.diff
LOG: [NFC][AMDGPU][CodeGen] Use ArrayRef in TargetLowering functions
Based on D123467.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D124508
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 0b88be99c4d1..6d3a3c10f693 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -128,49 +128,27 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
// There are no 64-bit extloads. These should be done as a 32-bit extload and
// an extension to 64-bit.
- for (MVT VT : MVT::integer_valuetypes()) {
- setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
- }
+ for (MVT VT : MVT::integer_valuetypes())
+ setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, VT,
+ Expand);
for (MVT VT : MVT::integer_valuetypes()) {
if (VT == MVT::i64)
continue;
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
-
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
-
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
+ for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) {
+ setLoadExtAction(Op, VT, MVT::i1, Promote);
+ setLoadExtAction(Op, VT, MVT::i8, Legal);
+ setLoadExtAction(Op, VT, MVT::i16, Legal);
+ setLoadExtAction(Op, VT, MVT::i32, Expand);
+ }
}
- for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
- }
+ for (MVT VT : MVT::integer_fixedlen_vector_valuetypes())
+ for (auto MemVT :
+ {MVT::v2i8, MVT::v4i8, MVT::v2i16, MVT::v3i16, MVT::v4i16})
+ setLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}, VT, MemVT,
+ Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
@@ -305,229 +283,125 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand);
setTruncStoreAction(MVT::v16i64, MVT::v16i1, Expand);
- setOperationAction(ISD::Constant, MVT::i32, Legal);
- setOperationAction(ISD::Constant, MVT::i64, Legal);
- setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
- setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
+ setOperationAction(ISD::Constant, {MVT::i32, MVT::i64}, Legal);
+ setOperationAction(ISD::ConstantFP, {MVT::f32, MVT::f64}, Legal);
- setOperationAction(ISD::BR_JT, MVT::Other, Expand);
- setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction({ISD::BR_JT, ISD::BRIND}, MVT::Other, Expand);
// This is totally unsupported, just custom lower to produce an error.
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
// Library functions. These default to Expand, but we have instructions
// for them.
- setOperationAction(ISD::FCEIL, MVT::f32, Legal);
- setOperationAction(ISD::FEXP2, MVT::f32, Legal);
- setOperationAction(ISD::FPOW, MVT::f32, Legal);
- setOperationAction(ISD::FLOG2, MVT::f32, Legal);
- setOperationAction(ISD::FABS, MVT::f32, Legal);
- setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
- setOperationAction(ISD::FRINT, MVT::f32, Legal);
- setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
- setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
- setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
-
- setOperationAction(ISD::FROUND, MVT::f32, Custom);
- setOperationAction(ISD::FROUND, MVT::f64, Custom);
+ setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS,
+ ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM,
+ ISD::FMAXNUM},
+ MVT::f32, Legal);
- setOperationAction(ISD::FLOG, MVT::f32, Custom);
- setOperationAction(ISD::FLOG10, MVT::f32, Custom);
- setOperationAction(ISD::FEXP, MVT::f32, Custom);
+ setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom);
+ setOperationAction({ISD::FLOG, ISD::FLOG10, ISD::FEXP}, MVT::f32, Custom);
- setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
- setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
+ setOperationAction(ISD::FNEARBYINT, {MVT::f32, MVT::f64}, Custom);
- setOperationAction(ISD::FREM, MVT::f16, Custom);
- setOperationAction(ISD::FREM, MVT::f32, Custom);
- setOperationAction(ISD::FREM, MVT::f64, Custom);
+ setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom);
// Expand to fneg + fadd.
setOperationAction(ISD::FSUB, MVT::f64, Expand);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v6i32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v6f32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v7i32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v7f32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
- setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f16, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i16, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f16, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i16, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v6f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v6i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v7f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v7i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f64, Custom);
- setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i64, Custom);
+ setOperationAction(ISD::CONCAT_VECTORS,
+ {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32,
+ MVT::v5i32, MVT::v5f32, MVT::v6i32, MVT::v6f32,
+ MVT::v7i32, MVT::v7f32, MVT::v8i32, MVT::v8f32},
+ Custom);
+ setOperationAction(ISD::EXTRACT_SUBVECTOR,
+ {MVT::v2f16, MVT::v2i16, MVT::v4f16, MVT::v4i16,
+ MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32,
+ MVT::v4f32, MVT::v4i32, MVT::v5f32, MVT::v5i32,
+ MVT::v6f32, MVT::v6i32, MVT::v7f32, MVT::v7i32,
+ MVT::v8f32, MVT::v8i32, MVT::v16f32, MVT::v16i32,
+ MVT::v32f32, MVT::v32i32, MVT::v2f64, MVT::v2i64,
+ MVT::v3f64, MVT::v3i64, MVT::v4f64, MVT::v4i64,
+ MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64},
+ Custom);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
- setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
- setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
+ setOperationAction(ISD::FP_TO_FP16, {MVT::f64, MVT::f32}, Custom);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
for (MVT VT : ScalarIntVTs) {
// These should use [SU]DIVREM, so set them to expand
- setOperationAction(ISD::SDIV, VT, Expand);
- setOperationAction(ISD::UDIV, VT, Expand);
- setOperationAction(ISD::SREM, VT, Expand);
- setOperationAction(ISD::UREM, VT, Expand);
+ setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, VT,
+ Expand);
// GPU does not have divrem function for signed or unsigned.
- setOperationAction(ISD::SDIVREM, VT, Custom);
- setOperationAction(ISD::UDIVREM, VT, Custom);
+ setOperationAction({ISD::SDIVREM, ISD::UDIVREM}, VT, Custom);
// GPU does not have [S|U]MUL_LOHI functions as a single instruction.
- setOperationAction(ISD::SMUL_LOHI, VT, Expand);
- setOperationAction(ISD::UMUL_LOHI, VT, Expand);
+ setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, VT, Expand);
- setOperationAction(ISD::BSWAP, VT, Expand);
- setOperationAction(ISD::CTTZ, VT, Expand);
- setOperationAction(ISD::CTLZ, VT, Expand);
+ setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand);
// AMDGPU uses ADDC/SUBC/ADDE/SUBE
- setOperationAction(ISD::ADDC, VT, Legal);
- setOperationAction(ISD::SUBC, VT, Legal);
- setOperationAction(ISD::ADDE, VT, Legal);
- setOperationAction(ISD::SUBE, VT, Legal);
+ setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal);
}
// The hardware supports 32-bit FSHR, but not FSHL.
setOperationAction(ISD::FSHR, MVT::i32, Legal);
// The hardware supports 32-bit ROTR, but not ROTL.
- setOperationAction(ISD::ROTL, MVT::i32, Expand);
- setOperationAction(ISD::ROTL, MVT::i64, Expand);
+ setOperationAction(ISD::ROTL, {MVT::i32, MVT::i64}, Expand);
setOperationAction(ISD::ROTR, MVT::i64, Expand);
- setOperationAction(ISD::MULHU, MVT::i16, Expand);
- setOperationAction(ISD::MULHS, MVT::i16, Expand);
+ setOperationAction({ISD::MULHU, ISD::MULHS}, MVT::i16, Expand);
- setOperationAction(ISD::MUL, MVT::i64, Expand);
- setOperationAction(ISD::MULHU, MVT::i64, Expand);
- setOperationAction(ISD::MULHS, MVT::i64, Expand);
- setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
- setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
- setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
+ setOperationAction({ISD::MUL, ISD::MULHU, ISD::MULHS}, MVT::i64, Expand);
+ setOperationAction(
+ {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT},
+ MVT::i64, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
- setOperationAction(ISD::SMIN, MVT::i32, Legal);
- setOperationAction(ISD::UMIN, MVT::i32, Legal);
- setOperationAction(ISD::SMAX, MVT::i32, Legal);
- setOperationAction(ISD::UMAX, MVT::i32, Legal);
+ setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i32,
+ Legal);
- setOperationAction(ISD::CTTZ, MVT::i64, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
- setOperationAction(ISD::CTLZ, MVT::i64, Custom);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
+ setOperationAction(
+ {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF},
+ MVT::i64, Custom);
static const MVT::SimpleValueType VectorIntTypes[] = {
MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32};
for (MVT VT : VectorIntTypes) {
// Expand the following operations for the current type by default.
- setOperationAction(ISD::ADD, VT, Expand);
- setOperationAction(ISD::AND, VT, Expand);
- setOperationAction(ISD::FP_TO_SINT, VT, Expand);
- setOperationAction(ISD::FP_TO_UINT, VT, Expand);
- setOperationAction(ISD::MUL, VT, Expand);
- setOperationAction(ISD::MULHU, VT, Expand);
- setOperationAction(ISD::MULHS, VT, Expand);
- setOperationAction(ISD::OR, VT, Expand);
- setOperationAction(ISD::SHL, VT, Expand);
- setOperationAction(ISD::SRA, VT, Expand);
- setOperationAction(ISD::SRL, VT, Expand);
- setOperationAction(ISD::ROTL, VT, Expand);
- setOperationAction(ISD::ROTR, VT, Expand);
- setOperationAction(ISD::SUB, VT, Expand);
- setOperationAction(ISD::SINT_TO_FP, VT, Expand);
- setOperationAction(ISD::UINT_TO_FP, VT, Expand);
- setOperationAction(ISD::SDIV, VT, Expand);
- setOperationAction(ISD::UDIV, VT, Expand);
- setOperationAction(ISD::SREM, VT, Expand);
- setOperationAction(ISD::UREM, VT, Expand);
- setOperationAction(ISD::SMUL_LOHI, VT, Expand);
- setOperationAction(ISD::UMUL_LOHI, VT, Expand);
- setOperationAction(ISD::SDIVREM, VT, Expand);
- setOperationAction(ISD::UDIVREM, VT, Expand);
- setOperationAction(ISD::SELECT, VT, Expand);
- setOperationAction(ISD::VSELECT, VT, Expand);
- setOperationAction(ISD::SELECT_CC, VT, Expand);
- setOperationAction(ISD::XOR, VT, Expand);
- setOperationAction(ISD::BSWAP, VT, Expand);
- setOperationAction(ISD::CTPOP, VT, Expand);
- setOperationAction(ISD::CTTZ, VT, Expand);
- setOperationAction(ISD::CTLZ, VT, Expand);
- setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
- setOperationAction(ISD::SETCC, VT, Expand);
+ setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT,
+ ISD::FP_TO_UINT, ISD::MUL, ISD::MULHU,
+ ISD::MULHS, ISD::OR, ISD::SHL,
+ ISD::SRA, ISD::SRL, ISD::ROTL,
+ ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP,
+ ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV,
+ ISD::SREM, ISD::UREM, ISD::SMUL_LOHI,
+ ISD::UMUL_LOHI, ISD::SDIVREM, ISD::UDIVREM,
+ ISD::SELECT, ISD::VSELECT, ISD::SELECT_CC,
+ ISD::XOR, ISD::BSWAP, ISD::CTPOP,
+ ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE,
+ ISD::SETCC},
+ VT, Expand);
}
static const MVT::SimpleValueType FloatVectorTypes[] = {
MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32, MVT::v6f32, MVT::v7f32};
for (MVT VT : FloatVectorTypes) {
- setOperationAction(ISD::FABS, VT, Expand);
- setOperationAction(ISD::FMINNUM, VT, Expand);
- setOperationAction(ISD::FMAXNUM, VT, Expand);
- setOperationAction(ISD::FADD, VT, Expand);
- setOperationAction(ISD::FCEIL, VT, Expand);
- setOperationAction(ISD::FCOS, VT, Expand);
- setOperationAction(ISD::FDIV, VT, Expand);
- setOperationAction(ISD::FEXP2, VT, Expand);
- setOperationAction(ISD::FEXP, VT, Expand);
- setOperationAction(ISD::FLOG2, VT, Expand);
- setOperationAction(ISD::FREM, VT, Expand);
- setOperationAction(ISD::FLOG, VT, Expand);
- setOperationAction(ISD::FLOG10, VT, Expand);
- setOperationAction(ISD::FPOW, VT, Expand);
- setOperationAction(ISD::FFLOOR, VT, Expand);
- setOperationAction(ISD::FTRUNC, VT, Expand);
- setOperationAction(ISD::FMUL, VT, Expand);
- setOperationAction(ISD::FMA, VT, Expand);
- setOperationAction(ISD::FRINT, VT, Expand);
- setOperationAction(ISD::FNEARBYINT, VT, Expand);
- setOperationAction(ISD::FSQRT, VT, Expand);
- setOperationAction(ISD::FSIN, VT, Expand);
- setOperationAction(ISD::FSUB, VT, Expand);
- setOperationAction(ISD::FNEG, VT, Expand);
- setOperationAction(ISD::VSELECT, VT, Expand);
- setOperationAction(ISD::SELECT_CC, VT, Expand);
- setOperationAction(ISD::FCOPYSIGN, VT, Expand);
- setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
- setOperationAction(ISD::SETCC, VT, Expand);
- setOperationAction(ISD::FCANONICALIZE, VT, Expand);
+ setOperationAction(
+ {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD,
+ ISD::FCEIL, ISD::FCOS, ISD::FDIV, ISD::FEXP2,
+ ISD::FEXP, ISD::FLOG2, ISD::FREM, ISD::FLOG,
+ ISD::FLOG10, ISD::FPOW, ISD::FFLOOR, ISD::FTRUNC,
+ ISD::FMUL, ISD::FMA, ISD::FRINT, ISD::FNEARBYINT,
+ ISD::FSQRT, ISD::FSIN, ISD::FSUB, ISD::FNEG,
+ ISD::VSELECT, ISD::SELECT_CC, ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE,
+ ISD::SETCC, ISD::FCANONICALIZE},
+ VT, Expand);
}
// This causes using an unrolled select operation rather than expansion with
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index fb21fb96d80f..6e14f0b8ff8b 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -42,39 +42,26 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
computeRegisterProperties(Subtarget->getRegisterInfo());
// Legalize loads and stores to the private address space.
- setOperationAction(ISD::LOAD, MVT::i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
+ setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom);
// EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
// spaces, so it is custom lowered to handle those where it isn't.
- for (MVT VT : MVT::integer_valuetypes()) {
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
- setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
-
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
- setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
-
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
- setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
- }
+ for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD})
+ for (MVT VT : MVT::integer_valuetypes()) {
+ setLoadExtAction(Op, VT, MVT::i1, Promote);
+ setLoadExtAction(Op, VT, MVT::i8, Custom);
+ setLoadExtAction(Op, VT, MVT::i16, Custom);
+ }
// Workaround for LegalizeDAG asserting on expansion of i1 vector loads.
- setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
- setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
+ setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32,
+ MVT::v2i1, Expand);
- setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
- setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
+ setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32,
+ MVT::v4i1, Expand);
- setOperationAction(ISD::STORE, MVT::i8, Custom);
- setOperationAction(ISD::STORE, MVT::i32, Custom);
- setOperationAction(ISD::STORE, MVT::v2i32, Custom);
- setOperationAction(ISD::STORE, MVT::v4i32, Custom);
+ setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32},
+ Custom);
setTruncStoreAction(MVT::i32, MVT::i8, Custom);
setTruncStoreAction(MVT::i32, MVT::i16, Custom);
@@ -96,55 +83,34 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand);
// Set condition code actions
- setCondCodeAction(ISD::SETO, MVT::f32, Expand);
- setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
- setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
- setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
- setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
- setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
- setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
- setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
- setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
- setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
- setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
- setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
-
- setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
- setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
- setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
- setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
-
- setOperationAction(ISD::FCOS, MVT::f32, Custom);
- setOperationAction(ISD::FSIN, MVT::f32, Custom);
-
- setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
- setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
-
- setOperationAction(ISD::BR_CC, MVT::i32, Expand);
- setOperationAction(ISD::BR_CC, MVT::f32, Expand);
+ setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT,
+ ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE,
+ ISD::SETUGT, ISD::SETULT, ISD::SETULE},
+ MVT::f32, Expand);
+
+ setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT},
+ MVT::i32, Expand);
+
+ setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom);
+
+ setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand);
+
+ setOperationAction(ISD::BR_CC, {MVT::i32, MVT::f32}, Expand);
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
setOperationAction(ISD::FSUB, MVT::f32, Expand);
- setOperationAction(ISD::FCEIL, MVT::f64, Custom);
- setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
- setOperationAction(ISD::FRINT, MVT::f64, Custom);
- setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
+ setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FRINT, ISD::FFLOOR},
+ MVT::f64, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::i32}, Custom);
- setOperationAction(ISD::SETCC, MVT::i32, Expand);
- setOperationAction(ISD::SETCC, MVT::f32, Expand);
- setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
- setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
+ setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand);
+ setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64},
+ Custom);
- setOperationAction(ISD::SELECT, MVT::i32, Expand);
- setOperationAction(ISD::SELECT, MVT::f32, Expand);
- setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
- setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
+ setOperationAction(ISD::SELECT, {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32},
+ Expand);
// ADD, SUB overflow.
// TODO: turn these into Legal?
@@ -158,56 +124,43 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
if (!Subtarget->hasBFE())
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i1, MVT::v4i1}, Expand);
if (!Subtarget->hasBFE())
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i8, MVT::v4i8}, Expand);
if (!Subtarget->hasBFE())
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i16, MVT::v4i16}, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i32, MVT::v4i32}, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT,
+ {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT,
+ {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom);
// We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
// to be Legal/Custom in order to avoid library calls.
- setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
- setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
- setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
+ setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, MVT::i32,
+ Custom);
- if (!Subtarget->hasFMA()) {
- setOperationAction(ISD::FMA, MVT::f32, Expand);
- setOperationAction(ISD::FMA, MVT::f64, Expand);
- }
+ if (!Subtarget->hasFMA())
+ setOperationAction(ISD::FMA, {MVT::f32, MVT::f64}, Expand);
// FIXME: May need no denormals check
setOperationAction(ISD::FMAD, MVT::f32, Legal);
- if (!Subtarget->hasBFI()) {
+ if (!Subtarget->hasBFI())
// fcopysign can be done in a single instruction with BFI.
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- }
+ setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand);
if (!Subtarget->hasBCNT(32))
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
@@ -229,21 +182,17 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
- for (MVT VT : ScalarIntVTs) {
- setOperationAction(ISD::ADDC, VT, Expand);
- setOperationAction(ISD::SUBC, VT, Expand);
- setOperationAction(ISD::ADDE, VT, Expand);
- setOperationAction(ISD::SUBE, VT, Expand);
- }
+ for (MVT VT : ScalarIntVTs)
+ setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT,
+ Expand);
// LLVM will expand these to atomic_cmp_swap(0)
// and atomic_swap, respectively.
- setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
- setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
+ setOperationAction({ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE}, MVT::i32, Expand);
// We need to custom lower some of the intrinsics
- setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ setOperationAction({ISD::INTRINSIC_VOID, ISD::INTRINSIC_WO_CHAIN}, MVT::Other,
+ Custom);
setSchedulingPreference(Sched::Source);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 8080e9275334..3b65454967e1 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -153,27 +153,17 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setBooleanVectorContents(ZeroOrOneBooleanContent);
// We need to custom lower vector stores from local memory
- setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v6i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v7i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
- setOperationAction(ISD::LOAD, MVT::i1, Custom);
- setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
-
- setOperationAction(ISD::STORE, MVT::v2i32, Custom);
- setOperationAction(ISD::STORE, MVT::v3i32, Custom);
- setOperationAction(ISD::STORE, MVT::v4i32, Custom);
- setOperationAction(ISD::STORE, MVT::v5i32, Custom);
- setOperationAction(ISD::STORE, MVT::v6i32, Custom);
- setOperationAction(ISD::STORE, MVT::v7i32, Custom);
- setOperationAction(ISD::STORE, MVT::v8i32, Custom);
- setOperationAction(ISD::STORE, MVT::v16i32, Custom);
- setOperationAction(ISD::STORE, MVT::i1, Custom);
- setOperationAction(ISD::STORE, MVT::v32i32, Custom);
+ setOperationAction(ISD::LOAD,
+ {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
+ MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v16i32, MVT::i1,
+ MVT::v32i32},
+ Custom);
+
+ setOperationAction(ISD::STORE,
+ {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
+ MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v16i32, MVT::i1,
+ MVT::v32i32},
+ Custom);
setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
@@ -200,71 +190,47 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setTruncStoreAction(MVT::v8i64, MVT::v8i32, Expand);
setTruncStoreAction(MVT::v16i64, MVT::v16i32, Expand);
- setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
- setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
+ setOperationAction(ISD::GlobalAddress, {MVT::i32, MVT::i64}, Custom);
setOperationAction(ISD::SELECT, MVT::i1, Promote);
setOperationAction(ISD::SELECT, MVT::i64, Custom);
setOperationAction(ISD::SELECT, MVT::f64, Promote);
AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
- setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
+ setOperationAction(ISD::SELECT_CC,
+ {MVT::f32, MVT::i32, MVT::i64, MVT::f64, MVT::i1}, Expand);
setOperationAction(ISD::SETCC, MVT::i1, Promote);
- setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
- setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
+ setOperationAction(ISD::SETCC, {MVT::v2i1, MVT::v4i1}, Expand);
AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
- setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v3i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v3f32, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v4i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v5i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v5f32, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v6i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v6f32, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v7i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v7f32, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v8i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand);
- setOperationAction(ISD::TRUNCATE, MVT::v16i32, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand);
-
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
+ setOperationAction(ISD::TRUNCATE,
+ {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
+ MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v16i32},
+ Expand);
+ setOperationAction(ISD::FP_ROUND,
+ {MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32,
+ MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v16f32},
+ Expand);
+
+ setOperationAction(ISD::SIGN_EXTEND_INREG,
+ {MVT::v2i1, MVT::v4i1, MVT::v2i8, MVT::v4i8, MVT::v2i16,
+ MVT::v3i16, MVT::v4i16, MVT::Other},
+ Custom);
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
- setOperationAction(ISD::BR_CC, MVT::i1, Expand);
- setOperationAction(ISD::BR_CC, MVT::i32, Expand);
- setOperationAction(ISD::BR_CC, MVT::i64, Expand);
- setOperationAction(ISD::BR_CC, MVT::f32, Expand);
- setOperationAction(ISD::BR_CC, MVT::f64, Expand);
+ setOperationAction(ISD::BR_CC,
+ {MVT::i1, MVT::i32, MVT::i64, MVT::f32, MVT::f64}, Expand);
- setOperationAction(ISD::UADDO, MVT::i32, Legal);
- setOperationAction(ISD::USUBO, MVT::i32, Legal);
+ setOperationAction({ISD::UADDO, ISD::USUBO}, MVT::i32, Legal);
- setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
- setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
+ setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i32, Legal);
- setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
- setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
- setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
+ setOperationAction({ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}, MVT::i64,
+ Expand);
#if 0
- setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
- setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
+ setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i64, Legal);
#endif
// We only support LOAD/STORE and vector manipulation ops for vectors
@@ -374,94 +340,63 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v32i32);
}
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
+ setOperationAction(ISD::VECTOR_SHUFFLE,
+ {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32},
+ Expand);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, {MVT::v4f16, MVT::v4i16}, Custom);
// Avoid stack access for these.
// TODO: Generalize to more vector types.
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
-
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
-
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
+ setOperationAction({ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT},
+ {MVT::v2i16, MVT::v2f16, MVT::v2i8, MVT::v4i8, MVT::v8i8,
+ MVT::v4i16, MVT::v4f16},
+ Custom);
// Deal with vec3 vector operations when widened to vec4.
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
+ setOperationAction(ISD::INSERT_SUBVECTOR,
+ {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32}, Custom);
// Deal with vec5/6/7 vector operations when widened to vec8.
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6i32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6f32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v7i32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v7f32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
- setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
+ setOperationAction(ISD::INSERT_SUBVECTOR,
+ {MVT::v5i32, MVT::v5f32, MVT::v6i32, MVT::v6f32,
+ MVT::v7i32, MVT::v7f32, MVT::v8i32, MVT::v8f32},
+ Custom);
// BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
// and output demarshalling
- setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
- setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP, {MVT::i32, MVT::i64}, Custom);
// We can't return success/failure, only the old value,
// let LLVM add the comparison
- setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
- setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
+ setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, {MVT::i32, MVT::i64},
+ Expand);
- if (Subtarget->hasFlatAddressSpace()) {
- setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
- setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
- }
+ if (Subtarget->hasFlatAddressSpace())
+ setOperationAction(ISD::ADDRSPACECAST, {MVT::i32, MVT::i64}, Custom);
- setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
- setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
+ setOperationAction(ISD::BITREVERSE, {MVT::i32, MVT::i64}, Legal);
// FIXME: This should be narrowed to i32, but that only happens if i64 is
// illegal.
// FIXME: Should lower sub-i32 bswaps to bit-ops without v_perm_b32.
- setOperationAction(ISD::BSWAP, MVT::i64, Legal);
- setOperationAction(ISD::BSWAP, MVT::i32, Legal);
+ setOperationAction(ISD::BSWAP, {MVT::i64, MVT::i32}, Legal);
// On SI this is s_memtime and s_memrealtime on VI.
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
- setOperationAction(ISD::TRAP, MVT::Other, Custom);
- setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
+ setOperationAction({ISD::TRAP, ISD::DEBUGTRAP}, MVT::Other, Custom);
if (Subtarget->has16BitInsts()) {
- setOperationAction(ISD::FPOW, MVT::f16, Promote);
- setOperationAction(ISD::FPOWI, MVT::f16, Promote);
- setOperationAction(ISD::FLOG, MVT::f16, Custom);
- setOperationAction(ISD::FEXP, MVT::f16, Custom);
- setOperationAction(ISD::FLOG10, MVT::f16, Custom);
+ setOperationAction({ISD::FPOW, ISD::FPOWI}, MVT::f16, Promote);
+ setOperationAction({ISD::FLOG, ISD::FEXP, ISD::FLOG10}, MVT::f16, Custom);
}
if (Subtarget->hasMadMacF32Insts())
setOperationAction(ISD::FMAD, MVT::f32, Legal);
- if (!Subtarget->hasBFI()) {
+ if (!Subtarget->hasBFI())
// fcopysign can be done in a single instruction with BFI.
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- }
+ setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand);
if (!Subtarget->hasBCNT(32))
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
@@ -469,15 +404,11 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
if (!Subtarget->hasBCNT(64))
setOperationAction(ISD::CTPOP, MVT::i64, Expand);
- if (Subtarget->hasFFBH()) {
- setOperationAction(ISD::CTLZ, MVT::i32, Custom);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
- }
+ if (Subtarget->hasFFBH())
+ setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
- if (Subtarget->hasFFBL()) {
- setOperationAction(ISD::CTTZ, MVT::i32, Custom);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
- }
+ if (Subtarget->hasFFBL())
+ setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
// We only really have 32-bit BFE instructions (and 16-bit on VI).
//
@@ -491,84 +422,48 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setHasExtractBitsInsn(true);
// Clamp modifier on add/sub
- if (Subtarget->hasIntClamp()) {
- setOperationAction(ISD::UADDSAT, MVT::i32, Legal);
- setOperationAction(ISD::USUBSAT, MVT::i32, Legal);
- }
-
- if (Subtarget->hasAddNoCarry()) {
- setOperationAction(ISD::SADDSAT, MVT::i16, Legal);
- setOperationAction(ISD::SSUBSAT, MVT::i16, Legal);
- setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
- setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
- }
+ if (Subtarget->hasIntClamp())
+ setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Legal);
- setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
- setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
- setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
- setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
+ if (Subtarget->hasAddNoCarry())
+ setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, {MVT::i16, MVT::i32},
+ Legal);
+ setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, {MVT::f32, MVT::f64},
+ Custom);
// These are really only legal for ieee_mode functions. We should be avoiding
// them for functions that don't have ieee_mode enabled, so just say they are
// legal.
- setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
- setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
- setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
- setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
-
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE},
+ {MVT::f32, MVT::f64}, Legal);
- if (Subtarget->haveRoundOpsF64()) {
- setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
- setOperationAction(ISD::FCEIL, MVT::f64, Legal);
- setOperationAction(ISD::FRINT, MVT::f64, Legal);
- } else {
- setOperationAction(ISD::FCEIL, MVT::f64, Custom);
- setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
- setOperationAction(ISD::FRINT, MVT::f64, Custom);
- setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
- }
+ if (Subtarget->haveRoundOpsF64())
+ setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FRINT}, MVT::f64, Legal);
+ else
+ setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FRINT, ISD::FFLOOR},
+ MVT::f64, Custom);
setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
- setOperationAction(ISD::FSIN, MVT::f32, Custom);
- setOperationAction(ISD::FCOS, MVT::f32, Custom);
- setOperationAction(ISD::FDIV, MVT::f32, Custom);
+ setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom);
setOperationAction(ISD::FDIV, MVT::f64, Custom);
if (Subtarget->has16BitInsts()) {
- setOperationAction(ISD::Constant, MVT::i16, Legal);
-
- setOperationAction(ISD::SMIN, MVT::i16, Legal);
- setOperationAction(ISD::SMAX, MVT::i16, Legal);
+ setOperationAction({ISD::Constant, ISD::SMIN, ISD::SMAX, ISD::UMIN,
+ ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT},
+ MVT::i16, Legal);
- setOperationAction(ISD::UMIN, MVT::i16, Legal);
- setOperationAction(ISD::UMAX, MVT::i16, Legal);
-
- setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
- setOperationAction(ISD::ROTR, MVT::i16, Expand);
- setOperationAction(ISD::ROTL, MVT::i16, Expand);
-
- setOperationAction(ISD::SDIV, MVT::i16, Promote);
- setOperationAction(ISD::UDIV, MVT::i16, Promote);
- setOperationAction(ISD::SREM, MVT::i16, Promote);
- setOperationAction(ISD::UREM, MVT::i16, Promote);
- setOperationAction(ISD::UADDSAT, MVT::i16, Legal);
- setOperationAction(ISD::USUBSAT, MVT::i16, Legal);
-
- setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
-
- setOperationAction(ISD::CTTZ, MVT::i16, Promote);
- setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
- setOperationAction(ISD::CTLZ, MVT::i16, Promote);
- setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
- setOperationAction(ISD::CTPOP, MVT::i16, Promote);
+ setOperationAction({ISD::ROTR, ISD::ROTL, ISD::SELECT_CC, ISD::BR_CC},
+ MVT::i16, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
-
- setOperationAction(ISD::BR_CC, MVT::i16, Expand);
+ setOperationAction({ISD::SIGN_EXTEND, ISD::SDIV, ISD::UDIV, ISD::SREM,
+ ISD::UREM, ISD::BITREVERSE, ISD::CTTZ,
+ ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF,
+ ISD::CTPOP},
+ MVT::i16, Promote);
setOperationAction(ISD::LOAD, MVT::i16, Custom);
@@ -579,8 +474,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
- setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
- setOperationAction(ISD::FP_TO_UINT, MVT::i16, Custom);
+ setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, MVT::i16, Custom);
// F16 - Constant Actions.
setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
@@ -592,23 +486,18 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
// F16 - VOP1 Actions.
- setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
- setOperationAction(ISD::FCOS, MVT::f16, Custom);
- setOperationAction(ISD::FSIN, MVT::f16, Custom);
+ setOperationAction(
+ {ISD::FP_ROUND, ISD::FCOS, ISD::FSIN, ISD::FROUND, ISD::FPTRUNC_ROUND},
+ MVT::f16, Custom);
- setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
- setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
+ setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, MVT::i16, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
- setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
- setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
- setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
- setOperationAction(ISD::FROUND, MVT::f16, Custom);
- setOperationAction(ISD::FPTRUNC_ROUND, MVT::f16, Custom);
+ setOperationAction(
+ {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP},
+ MVT::f16, Promote);
// F16 - VOP2 Actions.
- setOperationAction(ISD::BR_CC, MVT::f16, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
+ setOperationAction({ISD::BR_CC, ISD::SELECT_CC}, MVT::f16, Expand);
setOperationAction(ISD::FDIV, MVT::f16, Custom);
@@ -642,16 +531,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
}
// v_perm_b32 can handle either of these.
- setOperationAction(ISD::BSWAP, MVT::i16, Legal);
- setOperationAction(ISD::BSWAP, MVT::v2i16, Legal);
+ setOperationAction(ISD::BSWAP, {MVT::i16, MVT::v2i16}, Legal);
setOperationAction(ISD::BSWAP, MVT::v4i16, Custom);
// XXX - Do these do anything? Vector constants turn into build_vector.
- setOperationAction(ISD::Constant, MVT::v2i16, Legal);
- setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
+ setOperationAction(ISD::Constant, {MVT::v2i16, MVT::v2f16}, Legal);
- setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
- setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
+ setOperationAction(ISD::UNDEF, {MVT::v2i16, MVT::v2f16}, Legal);
setOperationAction(ISD::STORE, MVT::v2i16, Promote);
AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
@@ -695,140 +581,87 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::STORE, MVT::v8f16, Promote);
AddPromotedToType(ISD::STORE, MVT::v8f16, MVT::v4i32);
- setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
- setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
+ setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},
+ MVT::v2i32, Expand);
setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
- setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
- setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
+ setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},
+ MVT::v4i32, Expand);
- setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Expand);
- setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Expand);
+ setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND},
+ MVT::v8i32, Expand);
- if (!Subtarget->hasVOP3PInsts()) {
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
- }
+ if (!Subtarget->hasVOP3PInsts())
+ setOperationAction(ISD::BUILD_VECTOR, {MVT::v2i16, MVT::v2f16}, Custom);
setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
// This isn't really legal, but this avoids the legalizer unrolling it (and
// allows matching fneg (fabs x) patterns)
setOperationAction(ISD::FABS, MVT::v2f16, Legal);
- setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
- setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
- setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
- setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
+ setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, MVT::f16, Custom);
+ setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE}, MVT::f16, Legal);
- setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
- setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
- setOperationAction(ISD::FMINNUM_IEEE, MVT::v8f16, Custom);
- setOperationAction(ISD::FMAXNUM_IEEE, MVT::v8f16, Custom);
+ setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE},
+ {MVT::v4f16, MVT::v8f16}, Custom);
- setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
- setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
- setOperationAction(ISD::FMINNUM, MVT::v8f16, Expand);
- setOperationAction(ISD::FMAXNUM, MVT::v8f16, Expand);
+ setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, {MVT::v4f16, MVT::v8f16},
+ Expand);
for (MVT Vec16 : { MVT::v8i16, MVT::v8f16 }) {
- setOperationAction(ISD::BUILD_VECTOR, Vec16, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec16, Custom);
+ setOperationAction(
+ {ISD::BUILD_VECTOR, ISD::EXTRACT_VECTOR_ELT, ISD::SCALAR_TO_VECTOR},
+ Vec16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, Vec16, Expand);
- setOperationAction(ISD::SCALAR_TO_VECTOR, Vec16, Custom);
}
}
if (Subtarget->hasVOP3PInsts()) {
- setOperationAction(ISD::ADD, MVT::v2i16, Legal);
- setOperationAction(ISD::SUB, MVT::v2i16, Legal);
- setOperationAction(ISD::MUL, MVT::v2i16, Legal);
- setOperationAction(ISD::SHL, MVT::v2i16, Legal);
- setOperationAction(ISD::SRL, MVT::v2i16, Legal);
- setOperationAction(ISD::SRA, MVT::v2i16, Legal);
- setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
- setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
- setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
- setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
-
- setOperationAction(ISD::UADDSAT, MVT::v2i16, Legal);
- setOperationAction(ISD::USUBSAT, MVT::v2i16, Legal);
- setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal);
- setOperationAction(ISD::SSUBSAT, MVT::v2i16, Legal);
-
- setOperationAction(ISD::FADD, MVT::v2f16, Legal);
- setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
- setOperationAction(ISD::FMA, MVT::v2f16, Legal);
-
- setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
- setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
-
- setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
-
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
-
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f16, Custom);
- setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
-
- for (MVT VT : { MVT::v4i16, MVT::v8i16 }) {
- // Split vector operations.
- setOperationAction(ISD::SHL, VT, Custom);
- setOperationAction(ISD::SRA, VT, Custom);
- setOperationAction(ISD::SRL, VT, Custom);
- setOperationAction(ISD::ADD, VT, Custom);
- setOperationAction(ISD::SUB, VT, Custom);
- setOperationAction(ISD::MUL, VT, Custom);
+ setOperationAction({ISD::ADD, ISD::SUB, ISD::MUL, ISD::SHL, ISD::SRL,
+ ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX,
+ ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT},
+ MVT::v2i16, Legal);
- setOperationAction(ISD::SMIN, VT, Custom);
- setOperationAction(ISD::SMAX, VT, Custom);
- setOperationAction(ISD::UMIN, VT, Custom);
- setOperationAction(ISD::UMAX, VT, Custom);
+ setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FMINNUM_IEEE,
+ ISD::FMAXNUM_IEEE, ISD::FCANONICALIZE},
+ MVT::v2f16, Legal);
- setOperationAction(ISD::UADDSAT, VT, Custom);
- setOperationAction(ISD::SADDSAT, VT, Custom);
- setOperationAction(ISD::USUBSAT, VT, Custom);
- setOperationAction(ISD::SSUBSAT, VT, Custom);
- }
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, {MVT::v2i16, MVT::v2f16},
+ Custom);
- for (MVT VT : { MVT::v4f16, MVT::v8f16 }) {
+ setOperationAction(ISD::VECTOR_SHUFFLE,
+ {MVT::v4f16, MVT::v4i16, MVT::v8f16, MVT::v8i16},
+ Custom);
+
+ for (MVT VT : {MVT::v4i16, MVT::v8i16})
// Split vector operations.
- setOperationAction(ISD::FADD, VT, Custom);
- setOperationAction(ISD::FMUL, VT, Custom);
- setOperationAction(ISD::FMA, VT, Custom);
- setOperationAction(ISD::FCANONICALIZE, VT, Custom);
- }
+ setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL, ISD::ADD, ISD::SUB,
+ ISD::MUL, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
+ ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT,
+ ISD::SSUBSAT},
+ VT, Custom);
- setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
- setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
+ for (MVT VT : {MVT::v4f16, MVT::v8f16})
+ // Split vector operations.
+ setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FCANONICALIZE},
+ VT, Custom);
- setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
- setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
+ setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, {MVT::v2f16, MVT::v4f16},
+ Custom);
setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
- setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
- setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
+ setOperationAction(ISD::SELECT, {MVT::v4i16, MVT::v4f16}, Custom);
if (Subtarget->hasPackedFP32Ops()) {
- setOperationAction(ISD::FADD, MVT::v2f32, Legal);
- setOperationAction(ISD::FMUL, MVT::v2f32, Legal);
- setOperationAction(ISD::FMA, MVT::v2f32, Legal);
- setOperationAction(ISD::FNEG, MVT::v2f32, Legal);
-
- for (MVT VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32 }) {
- setOperationAction(ISD::FADD, VT, Custom);
- setOperationAction(ISD::FMUL, VT, Custom);
- setOperationAction(ISD::FMA, VT, Custom);
- }
+ setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG},
+ MVT::v2f32, Legal);
+ setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA},
+ {MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32},
+ Custom);
}
}
- setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
- setOperationAction(ISD::FABS, MVT::v4f16, Custom);
+ setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v4f16, Custom);
if (Subtarget->has16BitInsts()) {
setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
@@ -837,56 +670,37 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
} else {
// Legalization hack.
- setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
- setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
-
- setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
- setOperationAction(ISD::FABS, MVT::v2f16, Custom);
- }
-
- for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8,
- MVT::v8i16, MVT::v8f16 }) {
- setOperationAction(ISD::SELECT, VT, Custom);
- }
-
- setOperationAction(ISD::SMULO, MVT::i64, Custom);
- setOperationAction(ISD::UMULO, MVT::i64, Custom);
-
- if (Subtarget->hasMad64_32()) {
- setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
- setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
- }
-
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
-
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3f16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3i16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4i16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
-
- setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::v3i16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::v3f16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
+ setOperationAction(ISD::SELECT, {MVT::v2i16, MVT::v2f16}, Custom);
+
+ setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v2f16, Custom);
+ }
+
+ setOperationAction(ISD::SELECT,
+ {MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8,
+ MVT::v8i16, MVT::v8f16},
+ Custom);
+
+ setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom);
+
+ if (Subtarget->hasMad64_32())
+ setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, MVT::i32, Custom);
+
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN,
+ {MVT::Other, MVT::f32, MVT::v4f32, MVT::i16, MVT::f16,
+ MVT::v2i16, MVT::v2f16},
+ Custom);
+
+ setOperationAction(ISD::INTRINSIC_W_CHAIN,
+ {MVT::v2f16, MVT::v2i16, MVT::v3f16, MVT::v3i16,
+ MVT::v4f16, MVT::v4i16, MVT::v8f16, MVT::Other, MVT::f16,
+ MVT::i16, MVT::i8},
+ Custom);
+
+ setOperationAction(ISD::INTRINSIC_VOID,
+ {MVT::Other, MVT::v2i16, MVT::v2f16, MVT::v3i16,
+ MVT::v3f16, MVT::v4f16, MVT::v4i16, MVT::f16, MVT::i16,
+ MVT::i8},
+ Custom);
setTargetDAGCombine({ISD::ADD,
ISD::ADDCARRY,
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