[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm requested changes to this revision.
arsenm added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1052
+    auto VGPR = Reg.first;
+    auto FI = Reg.second;
+    if (!FI)
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No auto


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:496
+  using LaneVGPRsMap = MapVector<Register, Optional<int>>;
+  LaneVGPRsMap LaneVGPRs;
 
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Needs a comment for what lane VGPRs are


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192