[PATCH] D125639: [NVPTX] Enable AtomicExpandPass for NVPTX

[Shilei Tian via Phabricator via llvm-commits]

tianshilei1992 added inline comments.


================
Comment at: llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp:5160
+    default:
+      return AtomicExpansionKind::CmpXChg;
+    }
----------------
tra wrote:
> Can we handle types other than 32 and 64-bit? If yes, we need tests at least for some of them (i8/i16/f16/i128). If not, this should probably be `llvm_unreachable()`.
This is quite interesting. I don't think CUDA can generate that kind of code, but OpenMP can. However, for other types, like `i16`, with the atomic expand, it's just converted to `AtomicCmpSwap` of type `i16`, and then the isel crashed. For now, I guess the best way is to use `llvm_unreachable` for other cases. In the long term, we may want to support the expansion of types with different bitwidth, but I don't have a clear idea how that would work. Otherwise, we will have to tell the front end that some types are not supported, which kind of breaks the assumption that front end can emit target agnostic code.


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  https://reviews.llvm.org/D125639/new/

https://reviews.llvm.org/D125639