[PATCH] D125700: [AMDGPU][GFX9] Support base+soffset+offset SMEM loads.

Mon May 16 23:57:57 PDT 2022

kosarev added inline comments.

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Comment at: llvm/test/MC/AMDGPU/gfx9_asm_smem.s:126

+s_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345
+// CHECK: [0x81,0x42,0x06,0xc0,0x45,0x23,0x01,0x00]
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arsenm wrote:
> An unaligned offset is suspicious looking but technically not wrong
I assume we are only interested in how instructions are getting encoded here, so no need for them to look very realistic?

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Comment at: llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt:10077

+# CHECK: s_load_dword s5, s[2:3], s0 offset:0x12345 ; encoding: [0x41,0x41,0x02,0xc0,0x45,0x23,0x01,0x00]
+0x41,0x41,0x02,0xc0,0x45,0x23,0x01,0x00
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rampitec wrote:
> arsenm wrote:
> > rampitec wrote:
> > > Is there a decoding conflict which requires to use brackets here? Something from the TODO list?
> > I'm not sure what this question means. The encoding is always printed in brackets?
> Printed yes. But disasm tests do not use brackets. These are needed in a stream of bytes when dis cannot find out a boundaries of an instruction itself, and that is usually an indication of disam conflict between subtargets.
I too see no bracketed input bytes here, only printed ones. May this be the case that you just see them on a separate line because of the larger length of the instruction?

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125700/new/

https://reviews.llvm.org/D125700