[llvm] 74f6ded - [AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon May 16 09:38:26 PDT 2022
Author: Craig Topper
Date: 2022-05-16T09:28:11-07:00
New Revision: 74f6ded49d8cc745cb28b74e57346d948bac2b2d
URL: https://github.com/llvm/llvm-project/commit/74f6ded49d8cc745cb28b74e57346d948bac2b2d
DIFF: https://github.com/llvm/llvm-project/commit/74f6ded49d8cc745cb28b74e57346d948bac2b2d.diff
LOG: [AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC
This bug is in generic DAG combine and easily reproducible on many
targets.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D125640
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-rev.ll
llvm/test/CodeGen/ARM/rev.ll
llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
llvm/test/CodeGen/Thumb/rev.ll
llvm/test/CodeGen/X86/bswap.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index d4f4c26c53eea..7220abf14c878 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -949,3 +949,24 @@ entry:
%7 = or i64 %5, %6
ret i64 %7
}
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev w8, w0
+; CHECK-NEXT: asr w0, w8, #16
+; CHECK-NEXT: ret
+;
+; GISEL-LABEL: pr55484:
+; GISEL: // %bb.0:
+; GISEL-NEXT: lsl w8, w0, #8
+; GISEL-NEXT: orr w8, w8, w0, lsr #8
+; GISEL-NEXT: sxth w0, w8
+; GISEL-NEXT: ret
+ %2 = lshr i32 %0, 8
+ %3 = shl i32 %0, 8
+ %4 = or i32 %2, %3
+ %5 = trunc i32 %4 to i16
+ %6 = sext i16 %5 to i32
+ ret i32 %6
+}
diff --git a/llvm/test/CodeGen/ARM/rev.ll b/llvm/test/CodeGen/ARM/rev.ll
index d7875af04e9c5..d92794124bdf7 100644
--- a/llvm/test/CodeGen/ARM/rev.ll
+++ b/llvm/test/CodeGen/ARM/rev.ll
@@ -181,3 +181,16 @@ entry:
%conv3 = call i16 @llvm.bswap.i16(i16 %v)
ret i16 %conv3
}
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: revsh r0, r0
+; CHECK-NEXT: bx lr
+ %2 = lshr i32 %0, 8
+ %3 = shl i32 %0, 8
+ %4 = or i32 %2, %3
+ %5 = trunc i32 %4 to i16
+ %6 = sext i16 %5 to i32
+ ret i32 %6
+}
diff --git a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
index 61543f5c9273b..22612fcf76419 100644
--- a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
@@ -1635,3 +1635,77 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind {
%tmp2 = call i64 @llvm.bswap.i64(i64 %tmp)
ret i64 %tmp2
}
+
+define i32 @pr55484(i32 %0) {
+; RV32I-LABEL: pr55484:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a1, a0, 8
+; RV32I-NEXT: slli a0, a0, 8
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srai a0, a0, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: pr55484:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a1, a0, 8
+; RV64I-NEXT: slli a0, a0, 8
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srai a0, a0, 48
+; RV64I-NEXT: ret
+;
+; RV32ZBB-LABEL: pr55484:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: rev8 a0, a0
+; RV32ZBB-NEXT: srai a0, a0, 16
+; RV32ZBB-NEXT: ret
+;
+; RV64ZBB-LABEL: pr55484:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: rev8 a0, a0
+; RV64ZBB-NEXT: srai a0, a0, 48
+; RV64ZBB-NEXT: ret
+;
+; RV32ZBKB-LABEL: pr55484:
+; RV32ZBKB: # %bb.0:
+; RV32ZBKB-NEXT: srli a1, a0, 8
+; RV32ZBKB-NEXT: slli a0, a0, 8
+; RV32ZBKB-NEXT: or a0, a1, a0
+; RV32ZBKB-NEXT: slli a0, a0, 16
+; RV32ZBKB-NEXT: srai a0, a0, 16
+; RV32ZBKB-NEXT: ret
+;
+; RV64ZBKB-LABEL: pr55484:
+; RV64ZBKB: # %bb.0:
+; RV64ZBKB-NEXT: srli a1, a0, 8
+; RV64ZBKB-NEXT: slli a0, a0, 8
+; RV64ZBKB-NEXT: or a0, a1, a0
+; RV64ZBKB-NEXT: slli a0, a0, 48
+; RV64ZBKB-NEXT: srai a0, a0, 48
+; RV64ZBKB-NEXT: ret
+;
+; RV32ZBP-LABEL: pr55484:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: srli a1, a0, 8
+; RV32ZBP-NEXT: slli a0, a0, 8
+; RV32ZBP-NEXT: or a0, a1, a0
+; RV32ZBP-NEXT: slli a0, a0, 16
+; RV32ZBP-NEXT: srai a0, a0, 16
+; RV32ZBP-NEXT: ret
+;
+; RV64ZBP-LABEL: pr55484:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: srli a1, a0, 8
+; RV64ZBP-NEXT: slli a0, a0, 8
+; RV64ZBP-NEXT: or a0, a1, a0
+; RV64ZBP-NEXT: slli a0, a0, 48
+; RV64ZBP-NEXT: srai a0, a0, 48
+; RV64ZBP-NEXT: ret
+ %2 = lshr i32 %0, 8
+ %3 = shl i32 %0, 8
+ %4 = or i32 %2, %3
+ %5 = trunc i32 %4 to i16
+ %6 = sext i16 %5 to i32
+ ret i32 %6
+}
diff --git a/llvm/test/CodeGen/Thumb/rev.ll b/llvm/test/CodeGen/Thumb/rev.ll
index 9ac65bf5c8eaf..e04f5d785335e 100644
--- a/llvm/test/CodeGen/Thumb/rev.ll
+++ b/llvm/test/CodeGen/Thumb/rev.ll
@@ -63,3 +63,16 @@ entry:
%conv8 = ashr exact i32 %sext, 16
ret i32 %conv8
}
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: revsh r0, r0
+; CHECK-NEXT: bx lr
+ %2 = lshr i32 %0, 8
+ %3 = shl i32 %0, 8
+ %4 = or i32 %2, %3
+ %5 = trunc i32 %4 to i16
+ %6 = sext i16 %5 to i32
+ ret i32 %6
+}
diff --git a/llvm/test/CodeGen/X86/bswap.ll b/llvm/test/CodeGen/X86/bswap.ll
index 6af70c614c8e7..16f68a327f44a 100644
--- a/llvm/test/CodeGen/X86/bswap.ll
+++ b/llvm/test/CodeGen/X86/bswap.ll
@@ -390,3 +390,25 @@ define i528 @large_promotion(i528 %A) nounwind {
ret i528 %Z
}
declare i528 @llvm.bswap.i528(i528)
+
+define i32 @pr55484(i32 %0) {
+; CHECK-LABEL: pr55484:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: bswapl %eax
+; CHECK-NEXT: sarl $16, %eax
+; CHECK-NEXT: retl
+;
+; CHECK64-LABEL: pr55484:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: bswapl %eax
+; CHECK64-NEXT: sarl $16, %eax
+; CHECK64-NEXT: retq
+ %2 = lshr i32 %0, 8
+ %3 = shl i32 %0, 8
+ %4 = or i32 %2, %3
+ %5 = trunc i32 %4 to i16
+ %6 = sext i16 %5 to i32
+ ret i32 %6
+}
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