[PATCH] D125310: [AArch64][RISCV][SelectionDAG] Support VECREDUCE_ADD mask operations

[WangLian via Phabricator via llvm-commits]

Jimerlife marked an inline comment as done.
Jimerlife added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5315
+  case ISD::VECREDUCE_ADD:
+    // If it is VECREDUCE_ADD mask operation then turn it to VECREDUCE_XOR
+    if (Operand.getValueType().getScalarType() == MVT::i1)
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paulwalker-arm wrote:
> This comment doesn't offer any real value. None of the canonicalisation above and below this one are commented so perhaps no comment it necessary.
Thanks, I removed this comment


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https://reviews.llvm.org/D125310