[PATCH] D125310: [AArch64][RISCV][SelectionDAG] Support VECREDUCE_ADD mask operations

[WangLian via Phabricator via llvm-commits]

Jimerlife updated this revision to Diff 429597.
Jimerlife added a comment.

address comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125310/new/

https://reviews.llvm.org/D125310

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

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