[PATCH] D125552: [RISCV] Add llvm.read.register support for vlenb

Fri May 13 09:58:41 PDT 2022

reames added a comment.

In D125552#3511824 <https://reviews.llvm.org/D125552#3511824>, @reames wrote:

> In D125552#3511820 <https://reviews.llvm.org/D125552#3511820>, @craig.topper wrote:
>
>> Should we eventually implement something like AArch64DAGToDAGISel::tryReadRegister?
>
> I think that basically comes down to a question of whether we think having the ccsr exposed earlier than COPY elimination is helpful.  I don't currently have a strong opinion on that, but would lean towards using the generic COPY through optimization.

This is absolutely what I did.  Thanks!  Fixed properly in 853fa8ee <https://reviews.llvm.org/rG853fa8ee225edf2d0de94b0dcbd31bea916e825e>.  Though I am surprised the register type auto-converts to something TII accepts...

Repository:
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  https://reviews.llvm.org/D125552/new/

https://reviews.llvm.org/D125552