[PATCH] D125552: [RISCV] Add llvm.read.register support for vlenb

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 13 08:30:09 PDT 2022


reames created this revision.
reames added reviewers: craig.topper, frasercrmck, kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, asb, hiraditya, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

This patch adds minimal support for lowering an read.register intrinsic with vlenb as the argument.  Note that vlenb is an implementation constant, so it is never allocatable.

This was split off a patch to eventually replace PseudoReadVLENB with a COPY MI because doing so revealed a couple of optimization opportunities which really seemed to warrant individual patches and tests.  To write those patches, I need a way to write the tests involving vlenb, and read.register seemed like the right testing hook.

A couple notes for reviewers on oddities (things we should maybe fix infrastructure in other patches):

- InstrEmitter will crash when lowering a copy from a physical register if that physical register is not a member of some register class.  I didn't study the code closely, but on the surface this seems odd.  I worked around this by adding a dummy register class, and assuming others agree, will use it's removal as the test for a change to InstrEmitter.
- I couldn't figure out a robust way to translate from CSR register defs to the sysreg number.  Oddly, getName() on VLENB returns EH_LABEL?   I suspect we have something missing elsewhere.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125552

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/get-register-noreserve.ll


Index: llvm/test/CodeGen/RISCV/get-register-noreserve.ll
===================================================================
--- llvm/test/CodeGen/RISCV/get-register-noreserve.ll
+++ llvm/test/CodeGen/RISCV/get-register-noreserve.ll
@@ -31,8 +31,20 @@
   ret i32 %sp
 }
 
+define i32 @get_csr_vlenb() nounwind {
+; CHECK-LABEL: get_csr_vlenb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    ret
+entry:
+  %sp = call i32 @llvm.read_register.i32(metadata !2)
+  ret i32 %sp
+}
+
+
 declare i32 @llvm.read_register.i32(metadata) nounwind
 declare void @llvm.write_register.i32(metadata, i32) nounwind
 
 !0 = !{!"sp\00"}
 !1 = !{!"x4\00"}
+!2 = !{!"vlenb"}
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -462,6 +462,12 @@
                DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
 }
 
+def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
+                          (add VTYPE, VL, VLENB)> {
+  let RegInfos = XLenRI;
+}
+
+
 foreach m = [1, 2, 4] in {
   foreach n = NFList<m>.L in {
     def "VN" # n # "M" # m # "NoV0": RegisterTuples<
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -102,6 +102,7 @@
   markSuperRegs(Reserved, RISCV::VTYPE);
   markSuperRegs(Reserved, RISCV::VXSAT);
   markSuperRegs(Reserved, RISCV::VXRM);
+  markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
 
   // Floating point environment registers.
   markSuperRegs(Reserved, RISCV::FRM);
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -264,6 +264,16 @@
     return;
   }
 
+  // Handle copy from csr
+  // TODO: Handle sysreg lookup generically and remove vlenb restriction.
+  if (RISCV::VCSRRegClass.contains(SrcReg) && SrcReg == RISCV::VLENB &&
+      RISCV::GPRRegClass.contains(DstReg)) {
+    BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg)
+      .addImm(RISCVSysReg::lookupSysRegByName("VLENB")->Encoding)
+      .addReg(RISCV::X0);
+    return;
+  }
+
   // FPR->FPR copies and VR->VR copies.
   unsigned Opc;
   bool IsScalableVector = true;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D125552.429248.patch
Type: text/x-patch
Size: 2480 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220513/6f0daefd/attachment.bin>


More information about the llvm-commits mailing list