[PATCH] D125377: [AArch64] Order STP Q's by ascending address

[Andre Vieira via Phabricator via llvm-commits]

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Hi,

This patch adds an AArch64 specific PostRA MachineScheduler to try to schedule STP Q's to the same base-address in ascending order of offsets. We have found this to improve performance on Neoverse N1 and should not hurt other AArch64 cores.


https://reviews.llvm.org/D125377

Files:
  llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp
  llvm/lib/Target/AArch64/AArch64MachineScheduler.h
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/lib/Target/AArch64/CMakeLists.txt
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
  llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
  llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn

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