[PATCH] D124464: [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18790-18793
+  case AArch64ISD::ADDS:
+    return performFlagSettingCombine(N, DCI, ISD::ADD);
+  case AArch64ISD::SUBS:
+    return performFlagSettingCombine(N, DCI, ISD::SUB);
----------------
Kmeakin wrote:
> paulwalker-arm wrote:
> > Do the `ADDS` and `SUBS` cases occur today? If they do then can we have some tests.
> Could not generate any tests where these transforms would fire, but its worth leaving these in for completeness: they might become applicable later if new transforms add the opportunity for them to apply. 
I disagree. Although the code is likely fine if there's no way to test it then it's just stale, potentially buggy code that bloats the compiler.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18852-18853
     return performCSELCombine(N, DCI, DAG);
-  case AArch64ISD::ANDS:
-    return performANDSCombine(N, DCI);
   case AArch64ISD::DUP:
----------------
Is there a good reason to move this code?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124464/new/

https://reviews.llvm.org/D124464