[PATCH] D124464: [AArch64] Replace `performANDSCombine` with `performFlagSettingCombine`.

[Karl Meakin via Phabricator via llvm-commits]

Kmeakin marked 2 inline comments as done.
Kmeakin added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17773
+  if (SDNode *Generic = DCI.DAG.getNodeIfExists(
+          GenericOpcode, DCI.DAG.getVTList(VT), {LHS, RHS}))
+    DCI.CombineTo(Generic, SDValue(N, 0));
----------------
paulwalker-arm wrote:
> Should this be `{N->ops()}` to support the `ADC` case? Is it possible to write tests for the new opcode cases?
I did try thi


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17773
+  if (SDNode *Generic = DCI.DAG.getNodeIfExists(
+          GenericOpcode, DCI.DAG.getVTList(VT), {LHS, RHS}))
+    DCI.CombineTo(Generic, SDValue(N, 0));
----------------
Kmeakin wrote:
> paulwalker-arm wrote:
> > Should this be `{N->ops()}` to support the `ADC` case? Is it possible to write tests for the new opcode cases?
> I did try thi
I couldn't find a way to construct an `ArrayRef<SDValue>` that would live long enough: the ArrayRef would get dropped at the end of the function while the `Generic` node still held a reference to its contents, leading to a segfault later. Suggest to leave it as is for now. 


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18790-18793
+  case AArch64ISD::ADDS:
+    return performFlagSettingCombine(N, DCI, ISD::ADD);
+  case AArch64ISD::SUBS:
+    return performFlagSettingCombine(N, DCI, ISD::SUB);
----------------
paulwalker-arm wrote:
> Do the `ADDS` and `SUBS` cases occur today? If they do then can we have some tests.
Could not generate any tests where these transforms would fire, but its worth leaving these in for completeness: they might become applicable later if new transforms add the opportunity for them to apply. 


Repository:
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  https://reviews.llvm.org/D124464/new/

https://reviews.llvm.org/D124464