[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic added a comment.

In D123782#3498708 <https://reviews.llvm.org/D123782#3498708>, @dmgreen wrote:

> I can commit this for you if you don't have commit access yet. I would just need a "name <email at domain.com" for the attribution.

You can use "Rahul Anand R <rahul at rrlogic.co.in>" for the attribution.


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https://reviews.llvm.org/D123782