[PATCH] D123458: [LSR][RISCV] Improve test coverage for LSR in RISC-V

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/loop-strength-reduce-ivusers.ll:48
+; RV64-NEXT:  .LBB0_2: # %bb29.i38
+; RV64-NEXT:    # Parent Loop BB0_1 Depth=1
+; RV64-NEXT:    # => This Inner Loop Header: Depth=2
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craig.topper wrote:
> Why is this loop substantially simpler than the RV32 version? I suspect LSR doesn't run on RV64, but that means that LSR is making the RV32 loop worse than we would get without it?
Yes. LSR is generating running on RV32 and generating worse code.



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Comment at: llvm/test/CodeGen/RISCV/loop-strength-reduce-ivusers.ll:57
+bb4:		; preds = %bb4, %entry
+	br i1 true, label %bb5, label %bb4
+
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craig.topper wrote:
> Are these branch on true needed?
Updated test case with `simplifycfg`


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Comment at: llvm/test/CodeGen/RISCV/loop-strength-reduce-ivusers.ll:74
+	%1 = getelementptr [4 x [21 x double]], [4 x [21 x double]]* null, i32 0, i32 %0, i32 %sfb.314.i		; <double*> [#uses=1]
+	%2 = load double, double* %1, align 8		; <double> [#uses=0]
+	br i1 false, label %bb30.i41, label %bb33.i47
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craig.topper wrote:
> This load is dead. This whole test looks overly reduced.
Updated test case with `simplifycfg`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123458/new/

https://reviews.llvm.org/D123458