[PATCH] D124505: [RISCV] Add VL patterns for vector widening floating-point fused multiply-add instructions.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 6 19:22:48 PDT 2022
jacquesguan added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:946
+ (vti.Mask true_mask), VLOpFrag),
+ (riscv_fneg_vl (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
+ (vti.Mask true_mask), VLOpFrag)),
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craig.topper wrote:
> Is this longer than 80 columns?
Done.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124505/new/
https://reviews.llvm.org/D124505
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