[PATCH] D124986: [RISCV] Support VP_REDUCE_ADD mask operation
WangLian via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 5 18:58:26 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfb0d636f285b: [RISCV][SelectionDAG] Support VP_REDUCE_ADD mask operation. (authored by Jimerlife).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124986/new/
https://reviews.llvm.org/D124986
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
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