[PATCH] D124833: [RISCV] Optimize redundant vsetvli for Vector Mask-Register Logical Instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:702
+  default:
+    break;
+#define CASE_VMASK_OPCODES(suffix)                                             \
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`default: return false`? Then we don't need `IsMaskLogicalOp`


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:959
         // we need to insert a VSETVLI.
         // If this is a unit-stride or strided load/store, we may be able to use
         // the EMUL=(EEW/SEW)*LMUL relationship to avoid changing vtype.
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This comment could be updated


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1122
         // we need to insert a VSETVLI.
         // If this is a unit-stride or strided load/store, we may be able to use
         // the EMUL=(EEW/SEW)*LMUL relationship to avoid changing vtype.
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This comment too


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https://reviews.llvm.org/D124833