[PATCH] D124505: [RISCV] Add VL patterns for vector widening floating-point fused multiply-add instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:946
+                                             (vti.Mask true_mask), VLOpFrag),
+                   (riscv_fneg_vl (wti.Vector (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
+                                                                        (vti.Mask true_mask), VLOpFrag)),
----------------
Is this longer than 80 columns?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124505/new/

https://reviews.llvm.org/D124505