[PATCH] D124833: [RISCV] Optimize redundant vsetvli for Vector Mask-Register Logical Instructions.

[Zakk Chen via Phabricator via llvm-commits]

khchen created this revision.
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Skip to insert vsetvli if SEWLMULRatio had not been chagned.

Vector mask logical instructions are always unmasked and always updated
with a tail-agnostic policy.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124833

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

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