[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17464
     IsEQOrNE = true;
   }
 
----------------
You can get rid of the `IsEQOrNE` variable by adding

```
else
  return SDValue();
```


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17466
 
   if (IsEQOrNE &&
       (CTTZ.getOpcode() == ISD::CTTZ ||
----------------
Remove the IsEQOrNE using the suggestion above, then invert this to make an early out.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17498
+  SDValue Folded = foldCTTZ(N, DAG);
+  if (Folded.getNode() != nullptr)
+    return Folded;
----------------
```
if (SDValue Folded = foldCTTZ(N, DAG))
  return Folded;
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782