[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic marked 7 inline comments as done.
rahular-rrlogic added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17478
+        (CTTZ.getOpcode() == ISD::TRUNCATE &&
+          CTTZ.getOperand(0).getOpcode() == ISD::CTTZ))) {
+    if (isNullConstant(Zero) &&
----------------
dmgreen wrote:
> craig.topper wrote:
> > Technically, if you look through a truncate you need to know the truncate didn't drop any bits of the CTTZ result. But maybe AArch64ISD::SUBS and CSEL can only be created after type legalization so the only possible types are i32 and i64? I'm not an AArch64 expert so I don't know.
> Yeah I believe SUBS and CSEL will only be generated for legal types. Perhaps it is worth adding an assert just to be safe.
The type legalization does occur in this case which I checked via the debug output. I have added an assert anyway as @dmgreen suggested.


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  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782