[PATCH] D123581: [RISCV] Teach vsetvli insertion to handle VSETVLIInfo of vl-modified instruction.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D123581#3482481 <https://reviews.llvm.org/D123581#3482481>, @fakepaper56 wrote:

> In D123581#3445896 <https://reviews.llvm.org/D123581#3445896>, @craig.topper wrote:
>
>> Would it simplify things if the VLEFF pseudo instruction had the GPR output and the vector register output. And we expanded it PseudoReadVL after register allocation?
>
> Do you think should we change the output of VLEFF and VLSEGFF? I had tried to do that in my local, but I am confused that changing the output seems only benefit in the pass and we need to add more code in tablegen files and RISCVISelDAGToDAG.* than decreased code in the patch.

The InsertVSETVLI pass is complex and buggy. We've had 3 bugs in it in 2022. I want to reduce complexity here if possible.  Would adding SEW and LMUL from the VLEFF to the PseudoReadVL that gets emitted for VLEFF help without requiring us to give the VLEFF the GPR output?


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