[PATCH] D123581: [RISCV] Teach vsetvli insertion to handle VSETVLIInfo of vl-modified instruction.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added a comment.

In D123581#3445896 <https://reviews.llvm.org/D123581#3445896>, @craig.topper wrote:

> Would it simplify things if the VLEFF pseudo instruction had the GPR output and the vector register output. And we expanded it PseudoReadVL after register allocation?

Do you think should we change the output of VLEFF and VLSEGFF? I had tried to do that in my local, but I am confused that changing the output seems only benefit in the pass and we need to add more code in tablegen and RISCVISelDAGToDAG.* than decreased code in the patch.


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