[llvm] 3562f85 - [X86] SimplifyDemandedVectorEltsForTargetNode - fold (uniform) shift(0,x) -> 0
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 29 04:09:16 PDT 2022
Author: Simon Pilgrim
Date: 2022-04-29T12:08:47+01:00
New Revision: 3562f855b71e159908806d3152e81ef439d041ca
URL: https://github.com/llvm/llvm-project/commit/3562f855b71e159908806d3152e81ef439d041ca
DIFF: https://github.com/llvm/llvm-project/commit/3562f855b71e159908806d3152e81ef439d041ca.diff
LOG: [X86] SimplifyDemandedVectorEltsForTargetNode - fold (uniform) shift(0,x) -> 0
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 195bd98d943a..4689d9d14fb5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -40478,6 +40478,11 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
Depth + 1))
return true;
+ // Fold shift(0,x) -> 0
+ if (DemandedElts.isSubsetOf(KnownZero))
+ return TLO.CombineTo(
+ Op, getZeroVector(VT.getSimpleVT(), Subtarget, TLO.DAG, SDLoc(Op)));
+
// Aggressively peek through ops to get at the demanded elts.
if (!DemandedElts.isAllOnes())
if (SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts(
diff --git a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index 4c52da91a4e7..8ebc2640a8d6 100644
--- a/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -546,23 +546,20 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_nonsplat_eq:
; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
-; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,16776960,2147483648]
-; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
-; X86-SSE2-NEXT: psrld %xmm3, %xmm4
-; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[0,1,1,1,4,5,6,7]
-; X86-SSE2-NEXT: movdqa %xmm2, %xmm5
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
+; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm2[2,3,3,3,4,5,6,7]
+; X86-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,1,16776960,2147483648]
+; X86-SSE2-NEXT: movdqa %xmm4, %xmm5
; X86-SSE2-NEXT: psrld %xmm3, %xmm5
-; X86-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
-; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
-; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
-; X86-SSE2-NEXT: psrld %xmm3, %xmm4
-; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
-; X86-SSE2-NEXT: psrld %xmm1, %xmm2
-; X86-SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm4[1]
-; X86-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm2[0,3]
-; X86-SSE2-NEXT: andps %xmm5, %xmm0
+; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,1,1,4,5,6,7]
+; X86-SSE2-NEXT: movdqa %xmm4, %xmm3
+; X86-SSE2-NEXT: psrld %xmm2, %xmm3
+; X86-SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm5[1]
+; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[2,3,3,3,4,5,6,7]
+; X86-SSE2-NEXT: psrld %xmm1, %xmm4
+; X86-SSE2-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
+; X86-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,3],xmm3[0,3]
+; X86-SSE2-NEXT: andps %xmm4, %xmm0
; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; X86-SSE2-NEXT: retl
@@ -578,23 +575,20 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
;
; X64-SSE2-LABEL: vec_4xi32_nonsplat_eq:
; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
-; X64-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [0,1,16776960,2147483648]
-; X64-SSE2-NEXT: movdqa %xmm3, %xmm4
-; X64-SSE2-NEXT: psrld %xmm2, %xmm4
-; X64-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[0,1,1,1,4,5,6,7]
-; X64-SSE2-NEXT: movdqa %xmm3, %xmm5
-; X64-SSE2-NEXT: psrld %xmm2, %xmm5
-; X64-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
-; X64-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
-; X64-SSE2-NEXT: movdqa %xmm3, %xmm4
-; X64-SSE2-NEXT: psrld %xmm2, %xmm4
-; X64-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
-; X64-SSE2-NEXT: psrld %xmm1, %xmm3
-; X64-SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm4[1]
-; X64-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm3[0,3]
-; X64-SSE2-NEXT: andps %xmm5, %xmm0
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
+; X64-SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm2[2,3,3,3,4,5,6,7]
+; X64-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,1,16776960,2147483648]
+; X64-SSE2-NEXT: movdqa %xmm4, %xmm5
+; X64-SSE2-NEXT: psrld %xmm3, %xmm5
+; X64-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,1,1,4,5,6,7]
+; X64-SSE2-NEXT: movdqa %xmm4, %xmm3
+; X64-SSE2-NEXT: psrld %xmm2, %xmm3
+; X64-SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm5[1]
+; X64-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[2,3,3,3,4,5,6,7]
+; X64-SSE2-NEXT: psrld %xmm1, %xmm4
+; X64-SSE2-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
+; X64-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,3],xmm3[0,3]
+; X64-SSE2-NEXT: andps %xmm4, %xmm0
; X64-SSE2-NEXT: pxor %xmm1, %xmm1
; X64-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; X64-SSE2-NEXT: retq
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