[PATCH] D124231: [RISCV] Merge addi into load/store as there is a ADD between them
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 28 15:53:55 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2181
+ if (BaseOpIdx == 0) { // Load
+ if (Add) {
+ N = CurDAG->UpdateNodeOperands(N, Add, ImmOperand, N->getOperand(2));
----------------
Drop the curly braces here.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2188
+ } else { // Store
+ if (Add) {
+ N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), Add, ImmOperand,
----------------
And here.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124231/new/
https://reviews.llvm.org/D124231
More information about the llvm-commits
mailing list