[PATCH] D122769: [RISCV] Add a prepass to vsetvli insertion to propagate VLMAX vsetvli to the instructions.

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Any chance we can get more tests here?



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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:895
+    // Look for VLMAX vsetvlis.
+    if (!(isVectorConfigInstr(MI) && MI.getOperand(1).isReg() &&
+          MI.getOperand(1).getReg() == RISCV::X0 &&
----------------
Pulling out a helper function to match this would help readability for me.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:913
+      uint64_t TSFlags = UseMI.getDesc().TSFlags;
+      if (RISCVII::hasSEWOp(TSFlags) && RISCVII::hasVLOp(TSFlags)) {
+        unsigned NumOperands = UseMI.getNumExplicitOperands();
----------------
Can you use an early continue to reduce nesting here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D122769/new/

https://reviews.llvm.org/D122769