[PATCH] D124450: [AMDGPU] Remove hasOneUse check from scalar select pattern

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D124450#3474989 <https://reviews.llvm.org/D124450#3474989>, @foad wrote:

>> I'd love this to go in, but when I added the `hasOneUse()` check it was certainly needed.  If my old notes serve me well there was a crash in ctlz.ll test and I concluded this check was needed to avoid some shenanigans in the si-fix-sgpr-copies. I need to double check if the issue has been fixed or is just hidden.
>
> Since posting the patch I've found one out-of-tree case that fails to compile:
>
>   ; RUN: llc -march=amdgcn -mcpu=gfx1030 < %s
>   define amdgpu_cs void @main() {
>   bb:
>     %i = load i32, i32 addrspace(3)* null, align 16
>     br label %bb1
>   bb1:
>     %i2 = phi i32 [ 0, %bb ], [ %i9, %bb5 ]
>     br label %bb3
>   bb3:
>     %i4 = icmp eq i32 %i2, 0
>     br i1 %i4, label %bb5, label %bb3
>   bb5:
>     %i6 = icmp ult i32 0, %i
>     %i7 = sext i1 %i6 to i32
>     %i8 = add i32 %i7, 1
>     %i9 = and i32 %i8, %i7
>     br label %bb1
>   }

Can you recommit this test

> Shortly after this it crashes in `ScheduleDAGSDNodes::EmitPhysRegCopy` with: `MachineRegisterInfo.cpp:160: llvm::Register llvm::MachineRegisterInfo::createVirtualRegister(const llvm::TargetRegisterClass *, llvm::StringRef): Assertion 'RegClass->isAllocatable() && "Virtual register RegClass must be allocatable."' failed.`

The should be able to use SReg_32 which we do handle


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