[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17469
+  }
+  else if (CC == AArch64CC::NE && SUBS.getOpcode() == AArch64ISD::SUBS) {
+    Zero = N->getOperand(1);
----------------
`else` should be on the same line as the previous closing brace


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17481
+        isNullConstant(SUBS.getValue(1).getOperand(1))) {
+        SDValue X = CTTZ.getOpcode() == ISD::TRUNCATE ? CTTZ.getOperand(0).getOperand(0) : CTTZ.getOperand(0);
+      if(X == SUBS.getOperand(0)) {
----------------
This line is longer than 80 columns.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17482
+        SDValue X = CTTZ.getOpcode() == ISD::TRUNCATE ? CTTZ.getOperand(0).getOperand(0) : CTTZ.getOperand(0);
+      if(X == SUBS.getOperand(0)) {
+        unsigned BitWidth = CTTZ.getValueSizeInBits();
----------------
Space after `if`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782