[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic updated this revision to Diff 424924.
rahular-rrlogic marked an inline comment as done.
rahular-rrlogic added a comment.

Added condition to check if X in icmp and cttz are the same and added code to handle select (icmp ne X, 0), (cttz X), 0. Updated test for the same.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/table-based-cttz.ll

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