[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1267-1269
+  for (MachineBasicBlock &MBB : MF) {
+    for (auto &Reg : MFI->getLaneVGPRs())
+      MBB.addLiveIn(Reg.first);
----------------
cdevadas wrote:
> sebastian-ne wrote:
> > Why do we need these registers as a live-in to every block? (do we also need them as live-out if they should be alive everywhere?)
> These registers shouldn't be reused at the intermediate points and hence they must live-in all paths from the def point (prolog spills) to the use (the restores in the epilog).  There will be liveness verifier errors otherwise.
> I don't think the live-out is necessary.
 This is true for the globally reserved registers, like used for WWM. The VGPRs which are now allocated normally for SGPR spills do not need to be live in everywhere


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192