[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1267-1269
+  for (MachineBasicBlock &MBB : MF) {
+    for (auto &Reg : MFI->getLaneVGPRs())
+      MBB.addLiveIn(Reg.first);
----------------
sebastian-ne wrote:
> Why do we need these registers as a live-in to every block? (do we also need them as live-out if they should be alive everywhere?)
These registers shouldn't be reused at the intermediate points and hence they must live-in all paths from the def point (prolog spills) to the use (the restores in the epilog).  There will be liveness verifier errors otherwise.
I don't think the live-out is necessary.


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:505
   unsigned NumVGPRSpillLanes = 0;
-  SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
 
----------------
hsmhsm wrote:
> Are we still using the data structure `SGPRSpillVGPR`? If not, should not we delete it?
Yes, will clean it up.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192