[PATCH] D123578: [RISCV] Add sched to pseudo function call instructions

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added a comment.

In D123578#3470352 <https://reviews.llvm.org/D123578#3470352>, @zixuan-wu wrote:

> I think using two Write is not accurate because the latency are not added together but is the max one. It consumes resource simultaneously, but the expanded instructions auipc and jalr do have data dependency. 
> I think it should create a new SchedWrite such as WritePesudoCall and the cycle is sum up of WriteIALU and WriteJalr.
>
>   let Latency = 2 in
>   def : WriteRes<WritePesudoCall, [RocketUnitALU, RocketUnitB]>;
>
> Or we can make it simple with leveraging `WriteSequence` to create WritePesudoCall.
>
>   def WritePesudoCall : WriteSequence<[WriteIALU, WriteJalr]>;

I think it is unnecessary, since calls won't be part of scheduling regions.
As we discussed above, this patch just wants to make `llvm-mca` happy. :)


Repository:
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  https://reviews.llvm.org/D123578/new/

https://reviews.llvm.org/D123578