[PATCH] D123578: [RISCV] Add sched to pseudo function call instructions

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added a comment.

I think using two Write is not accurate because the latency are not added together but is the max one. It consumes resource simultaneously, but the expanded instructions auipc and jalr do have data dependency. 
I think it should create a new SchedWrite such as WritePesudoCall and the cycle is sum up of WriteIALU and WriteJalr.

  let Latency = 2 in
  def : WriteRes<WritePesudoCall, [RocketUnitALU, RocketUnitB]>;

Or we can make it simple with leveraging `WriteSequence` to create WritePesudoCall.

  def WritePesudoCall : WriteSequence<[WriteIALU, WriteJalr]>;


Repository:
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  https://reviews.llvm.org/D123578/new/

https://reviews.llvm.org/D123578