[PATCH] D124224: [AArch64][SVE] Add some logical operation DestructiveBinaryComm patterns

[Allen zhong via Phabricator via llvm-commits]

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Add DestructiveBinaryComm* patterns for ORR, EOR, AND and BIC.
The above instructions requires that the source and destination registers are
equal, so use movprfx should be beneficial to performance.


https://reviews.llvm.org/D124224

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll

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