[PATCH] D124144: [RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

This should be done in SelectionDAG::getNode not SelectionDAGBuilder so it happens any time a mask VP_ADD/VP_SUB/VP_MUL is created.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:7586
+  if (CheckVPMaskOp(Opcode, VTs)) {
+    Opcode = ISD::VP_XOR;
+  }
----------------
VP_MUL should be replaced with VP_AND.

0 * 0 -> 0
0 * 1 -> 0
1 * 0 -> 0
1 * 1 -> 1

The same as the truth table for AND.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124144/new/

https://reviews.llvm.org/D124144