[PATCH] D71492: [SCEV] Generate AddRec for trivial and LCSSA phis outside of loop header (WIP)

Bardia Mahjour via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 20 09:14:45 PDT 2022

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bmahjour abandoned this revision.
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This has been superseded by https://reviews.llvm.org/D71539


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  https://reviews.llvm.org/D71492/new/

https://reviews.llvm.org/D71492

Previous message: [PATCH] D122769: [RISCV] Add a prepass to vsetvli insertion to propagate VLMAX vsetvli to the instructions.
Next message: [llvm] 1fae4b4 - [InstCombine] Fold mul nuw+lshr to a single multiplication when the latter is a factor
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