[PATCH] D123264: [RISCV] Pre-RA expand pseudos pass

[Luís Marques via Phabricator via llvm-commits]

luismarques added inline comments.


================
Comment at: llvm/lib/CodeGen/MachineInstr.cpp:634
+  // If pre- or post-instruction symbols do not match then the two instructions
+  // are not identical.
+  if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
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jrtc27 wrote:
> This is overly strict in the specific case being addressed by this patch:
> ```
> 1: auipc a0, %pcrel_hi(foo)
>    lw a1, %pcrel_lo(1b)(a0)
>    addi a1, a1, 1
> 2: auipc a0, %pcrel_hi(foo)
>    sw a1, %pcrel_lo(2b)(a0)
> ```
> can legally be optimised to
> ```
> 1: auipc a0, %pcrel_hi(foo)
>    lw a1, %pcrel_lo(1b)(a0)
>    addi a1, a1, 1
>    sw a1, %pcrel_lo(1b)(a0)
> ```
That is a generic `MachineInstr` comparison function. We don't make use of it to reason about these address generation instructions sequences, it's here only to tighten the checks for other passes (namely the branch folder pass, possibly others) that would break once we start using pre-instruction symbols. So I guess it's fine as it? It's also not immediately obvious to me in which ways we could be more clever about the comparison and still keep it conservative enough to be target and "context" independent.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123264/new/

https://reviews.llvm.org/D123264