[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic updated this revision to Diff 423547.
rahular-rrlogic added a comment.

Updated test with description and made formatting changes.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782

Files:
  llvm/test/CodeGen/AArch64/table-based-cttz.ll


Index: llvm/test/CodeGen/AArch64/table-based-cttz.ll
===================================================================
--- llvm/test/CodeGen/AArch64/table-based-cttz.ll
+++ llvm/test/CodeGen/AArch64/table-based-cttz.ll
@@ -1,30 +1,32 @@
 ; RUN: llc -march=aarch64 < %s | FileCheck %s
 
+;; Check the transformation 
+;; CSEL 0, cttz, cc -> AND cttz numbits-1
+;; for cttz in the case of i32 and i64 respectively
+
 define i32 @ctz1(i32 %x) {
+;	CHECK: rbit w8, w0
+;	CHECK-NEXT: clz w8, w8
+;	CHECK-NEXT: and w0, w8, #0x1f
+;	CHECK-NEXT: ret
 entry:
   %0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
   %1 = icmp eq i32 %x, 0
   %2 = select i1 %1, i32 0, i32 %0
   ret i32 %2
-
-;CHECK: rbit w8, w0
-;CHECK-NEXT: clz w8, w8
-;CHECK-NEXT: and w0, w8, #0x1f
-;CHECK-NEXT: ret
 }
 
-define i32 @ctz4(i64 noundef %b) {
+define i32 @ctz2(i64 %x) {
+;	CHECK: rbit x8, x0
+;	CHECK-NEXT: clz x8, x8
+;	CHECK-NEXT: and w0, w8, #0x3f
+;	CHECK-NEXT: ret
 entry:
-  %0 = call i64 @llvm.cttz.i64(i64 %b, i1 true)
-  %1 = icmp eq i64 %b, 0
+  %0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
+  %1 = icmp eq i64 %x, 0
   %2 = trunc i64 %0 to i32
   %3 = select i1 %1, i32 0, i32 %2
   ret i32 %3
-
-;CHECK: rbit x8, x0
-;CHECK-NEXT: clz x8, x8
-;CHECK-NEXT: and w0, w8, #0x3f
-;CHECK-NEXT: ret
 }
 
 declare i32 @llvm.cttz.i32(i32, i1 immarg)


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