[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic updated this revision to Diff 423342.
rahular-rrlogic added a comment.

The condition for performing this optimization was modified to checking if the RHS of SUBS is 0 and if one of the values for the CSEL is a CTTZ.

Support for i64 was added.

Tests were added.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/table-based-cttz.ll


Index: llvm/test/CodeGen/AArch64/table-based-cttz.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/table-based-cttz.ll
@@ -0,0 +1,32 @@
+; RUN: llc -march=aarch64 < %s | FileCheck %s
+
+define i32 @ctz1(i32 %x) {
+entry:
+  %0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %1 = icmp eq i32 %x, 0
+  %2 = select i1 %1, i32 0, i32 %0
+  ret i32 %2
+
+;CHECK: rbit w8, w0
+;CHECK-NEXT: clz w8, w8
+;CHECK-NEXT: and w0, w8, #0x1f
+;CHECK-NEXT: ret
+}
+
+define i32 @ctz4(i64 noundef %b) {
+entry:
+  %0 = call i64 @llvm.cttz.i64(i64 %b, i1 true)
+  %1 = icmp eq i64 %b, 0
+  %2 = trunc i64 %0 to i32
+  %3 = select i1 %1, i32 0, i32 %2
+  ret i32 %3
+
+;CHECK: rbit x8, x0
+;CHECK-NEXT: clz x8, x8
+;CHECK-NEXT: and w0, w8, #0x3f
+;CHECK-NEXT: ret
+}
+
+declare i32 @llvm.cttz.i32(i32, i1 immarg)
+
+declare i64 @llvm.cttz.i64(i64, i1 immarg)
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17454,13 +17454,24 @@
   if (N->getOperand(0) == N->getOperand(1))
     return N->getOperand(0);
 
-  // CSEL cttz, 0, cc -> AND cttz 31
+  // CSEL 0, cttz, cc -> AND cttz numbits-1
   SDValue N1 = N->getOperand(1);
-  SDValue N2 = N->getOperand(2);
-  bool isZero = cast<ConstantSDNode>(N2.getNode())->isZero();
-  if (N1.getOpcode() == ISD::CTTZ && isZero) {
-    SDValue thirtyOne = DAG.getConstant(31, SDLoc(N), N1.getValueType());
-    return DAG.getNode(ISD::AND, SDLoc(N), N1.getValueType(), N1, thirtyOne);
+  SDValue N3 = N->getOperand(3);
+
+  if (N3.getOpcode() == AArch64ISD::SUBS &&
+      isNullConstant(N3.getValue(1).getOperand(1))) {
+    if (N1.getOpcode() == ISD::CTTZ) {
+      SDValue NumBitsMinusOne =
+          DAG.getConstant(31, SDLoc(N), N1.getValueType());
+      return DAG.getNode(ISD::AND, SDLoc(N), N1.getValueType(), N1,
+                         NumBitsMinusOne);
+    } else if (N1.getOpcode() == ISD::TRUNCATE &&
+               N1.getOperand(0).getOpcode() == ISD::CTTZ) {
+      SDValue NumBitsMinusOne =
+          DAG.getConstant(63, SDLoc(N), N1.getValueType());
+      return DAG.getNode(ISD::AND, SDLoc(N), N1.getValueType(), N1,
+                         NumBitsMinusOne);
+    }
   }
 
   return performCONDCombine(N, DCI, DAG, 2, 3);


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