[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

Djordje Todorovic via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 14 05:26:54 PDT 2022

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djtodoro added a comment.

Thanks for this! Please add test.


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  https://reviews.llvm.org/D123782/new/

https://reviews.llvm.org/D123782

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