[PATCH] D123782: [AArch64] Generate AND in place of CSEL for Table Based CTTZ lowering in -O3

[Rahul via Phabricator via llvm-commits]

rahular-rrlogic created this revision.
rahular-rrlogic added reviewers: craig.topper, djtodoro, dmgreen.
Herald added subscribers: StephenFan, hiraditya, kristof.beyls.
Herald added a project: All.
rahular-rrlogic requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch implements a for a target specific optimization on top of https://reviews.llvm.org/D113291?id=389938 that replaces the  `cmp` and `csel` with an `and`

Related submission and comments: https://reviews.llvm.org/D120462
Original issue: https://github.com/llvm/llvm-project/issues/45779


https://reviews.llvm.org/D123782

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp


Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17454,6 +17454,15 @@
   if (N->getOperand(0) == N->getOperand(1))
     return N->getOperand(0);
 
+  // CSEL cttz, 0, cc -> AND cttz 31
+  SDValue N1 = N->getOperand(1);
+  SDValue N2 = N->getOperand(2);
+  bool isZero = cast<ConstantSDNode>(N2.getNode())->isZero();
+  if (N1.getOpcode() == ISD::CTTZ && isZero) {
+    SDValue thirtyOne = DAG.getConstant(31, SDLoc(N), N1.getValueType());
+    return DAG.getNode(ISD::AND, SDLoc(N), N1.getValueType(), N1, thirtyOne);
+  }
+
   return performCONDCombine(N, DCI, DAG, 2, 3);
 }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D123782.422815.patch
Type: text/x-patch
Size: 761 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220414/8763e000/attachment.bin>