[PATCH] D122968: [AArch64][SelectionDAG] Add target-specific implementation of srem

chenglin.bi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 13 21:29:34 PDT 2022


bcl5980 added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4582
+        return OptimizedRem;
+    }
     SDValue OptimizedDiv =
----------------
efriedma wrote:
> Do we need to do something special for something like the following, to match the existing handling for div/rem pairs?  I guess it's only a couple instructions different either way, but maybe worth considering.
> 
> ```
> define void @sdivrem(i32 %x, i32* %ap, i32* %bp) {
>   %a = sdiv i32 %x, 4
>   %b = srem i32 %x, 4
>   store i32 %a, i32* %ap
>   store i32 %b, i32* %bp
>   ret void
> }
> ```
For now I have no AArch64 device to test, do we have some tools to verify instructions similar to alive2.llvm.org/ce/ on AArch64?
If no maybe I should use qemu to build a test environment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122968/new/

https://reviews.llvm.org/D122968



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