[PATCH] D122918: [RISCV][CodeGen] Support float-arith in Zfinx
Hugh Perkins via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 13 03:48:58 PDT 2022
hughperkins added a comment.
Also, not really part of this PR, but I don't know where else to put this. This code:
def FF : ExtInfo_rr<FExt, FPR32, FPR32>;
def FF_INX : ExtInfo_rr<ZfinxExt, FPR32INX, FPR32INX>;
def FX : ExtInfo_rr<FExt, FPR32, GPR>;
def FX_INX : ExtInfo_rr<ZfinxExt, FPR32INX, GPR>;
def FX_64 : ExtInfo_rr<F64Ext, FPR32, GPR>;
def FX_INX_64 : ExtInfo_rr<Zfinx64Ext, FPR32INX, GPR>;
def XF : ExtInfo_rr<FExt, GPR, FPR32>;
def XF_64 : ExtInfo_rr<F64Ext, GPR, FPR32>;
def XF_INX : ExtInfo_rr<ZfinxExt, GPR, FPR32INX>;
def XF_INX_64 : ExtInfo_rr<Zfinx64Ext, GPR, FPR32INX>;
... I feel it would be good to add a docstring explaining what this is, like e.g. something like:
Each of these definitions represents a single combination of register spaces.
For example, `FX` means that the destination register is a float register (`FPR32`), e.g. `ft1`,
and that the source register is a general `x` register (`GPR`), e.g. `x1`.
The `_INX` versions are for the `+zfinx` extension. In this case, `FPR32INX` is effectively a synonym in practice
for `GPR`. At least `FPR32INX` are emitted as general `x` registers, even though they 'look like' float registers
for much of the tablegen process.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D122918/new/
https://reviews.llvm.org/D122918
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