[PATCH] D123651: [AMDGPU][NFC] Organize code around reserving VGPR32 for AGPR copy.

[Mahesha S via Phabricator via llvm-commits]

hsmhsm created this revision.
hsmhsm added reviewers: rampitec, arsenm, cdevadas.
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hsmhsm requested review of this revision.
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This is an NFC patch in preparation to fix a bug related to always
reserving VGPR32 for AGPR copy.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123651

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp


Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -698,7 +698,10 @@
   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
   // VGPR available at all times.
   if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
-    reserveRegisterTuples(Reserved, AMDGPU::VGPR32);
+    auto reservedVGPR =
+        const_cast<SIMachineFunctionInfo *>(MFI)->reserveVGPRForAGPRCopy(
+            MaxNumVGPRs - 1);
+    reserveRegisterTuples(Reserved, reservedVGPR);
   }
 
   for (auto Reg : MFI->WWMReservedRegs) {
@@ -1553,8 +1556,8 @@
       assert(EltSize == 4);
 
       if (!TmpIntermediateVGPR) {
-        assert(MF->getRegInfo().isReserved(AMDGPU::VGPR32));
-        TmpIntermediateVGPR = AMDGPU::VGPR32;
+        TmpIntermediateVGPR = FuncInfo->getVGPRForAGPRCopy();
+        assert(MF->getRegInfo().isReserved(TmpIntermediateVGPR));
       }
       if (IsStore) {
         auto AccRead = BuildMI(MBB, MI, DL,
Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -493,6 +493,25 @@
   // frame, so save it here and add it to the RegScavenger later.
   Optional<int> ScavengeFI;
 
+private:
+  Register VGPRForAGPRCopy = AMDGPU::NoRegister;
+
+public:
+  Register getVGPRForAGPRCopy() const {
+    assert(VGPRForAGPRCopy &&
+           "Valid VGPR for AGPR copy must have been reserved by now");
+    return VGPRForAGPRCopy;
+  }
+
+  Register reserveVGPRForAGPRCopy(const unsigned HighestAvailableVGPR) {
+    if (VGPRForAGPRCopy)
+      return VGPRForAGPRCopy;
+
+    VGPRForAGPRCopy = AMDGPU::VGPR_32RegClass.getRegister(32);
+
+    return VGPRForAGPRCopy;
+  }
+
 public: // FIXME
   /// If this is set, an SGPR used for save/restore of the register used for the
   /// frame pointer.
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -614,7 +614,8 @@
   // Registers in the sequence are allocated contiguously so we can just
   // use register number to pick one of three round-robin temps.
   unsigned RegNo = DestReg % 3;
-  Register Tmp = AMDGPU::VGPR32;
+  Register Tmp =
+      MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getVGPRForAGPRCopy();
   assert(MBB.getParent()->getRegInfo().isReserved(Tmp) &&
          "VGPR used for an intermediate copy should have been reserved.");
 


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