[llvm] c33770d - [AMDGPU][DOC][NFC] Updated GFX10 assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 12 05:19:14 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-04-12T15:18:44+03:00
New Revision: c33770d87fd15cf6433a49f34aa31663726ea196
URL: https://github.com/llvm/llvm-project/commit/c33770d87fd15cf6433a49f34aa31663726ea196
DIFF: https://github.com/llvm/llvm-project/commit/c33770d87fd15cf6433a49f34aa31663726ea196.diff
LOG: [AMDGPU][DOC][NFC] Updated GFX10 assembler syntax description
The description has been updated to reflect AMDGPU MC changes:
- enabled literals for src0 of v_fmaak_f*, v_fmamk_f*, v_madak_f32, v_madmk_f32;
- enabled global_atomic_fcmpswap and global_atomic_fcmpswap_x2;
- enabled dlc with flat_atomic* and global_atomic_*.
Bug fixing and improvements:
- enabled s_wait_idle;
- enabled s_waitcnt_depctr;
- added description of s_waitcnt_depctr syntactic sugar;
- disabled SYSMSG_OP_HOST_TRAP_ACK (it is not supported on GFX10);
- corrected description of lgkmcnt (accept values from 0 to 63).
Added:
llvm/docs/AMDGPU/gfx10_imm16_73139a.rst
llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst
llvm/docs/AMDGPU/gfx10_m_254bcb.rst
llvm/docs/AMDGPU/gfx10_m_f5d306.rst
llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst
llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst
llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst
llvm/docs/AMDGPU/gfx10_sbase_020892.rst
llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst
llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst
llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst
llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst
llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst
llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst
llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst
llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst
llvm/docs/AMDGPU/gfx10_sdst_2e4c2a.rst
llvm/docs/AMDGPU/gfx10_sdst_362c37.rst
llvm/docs/AMDGPU/gfx10_sdst_3759f6.rst
llvm/docs/AMDGPU/gfx10_sdst_386c33.rst
llvm/docs/AMDGPU/gfx10_sdst_3bc700.rst
llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst
llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst
llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst
llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst
llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst
llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst
llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst
llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
llvm/docs/AMDGPU/gfx10_src_37d670.rst
llvm/docs/AMDGPU/gfx10_src_516946.rst
llvm/docs/AMDGPU/gfx10_src_823582.rst
llvm/docs/AMDGPU/gfx10_src_c27036.rst
llvm/docs/AMDGPU/gfx10_src_cf1cda.rst
llvm/docs/AMDGPU/gfx10_src_d5cd94.rst
llvm/docs/AMDGPU/gfx10_src_e0345d.rst
llvm/docs/AMDGPU/gfx10_src_e9e6db.rst
llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst
llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst
llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst
llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst
llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst
llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst
llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst
llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst
llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst
llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst
llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst
llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst
llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst
llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst
llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst
llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst
llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst
llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst
llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst
llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst
llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst
llvm/docs/AMDGPU/gfx10_vdata_15d255.rst
llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
llvm/docs/AMDGPU/gfx10_vdata_56f215.rst
llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst
llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
llvm/docs/AMDGPU/gfx10_vdata_c08393.rst
llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst
llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst
llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst
llvm/docs/AMDGPU/gfx10_vdst_463513.rst
llvm/docs/AMDGPU/gfx10_vdst_473a69.rst
llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst
llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
llvm/docs/AMDGPU/gfx10_vdst_69a144.rst
llvm/docs/AMDGPU/gfx10_vdst_719833.rst
llvm/docs/AMDGPU/gfx10_vdst_89680f.rst
llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst
llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst
llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst
llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst
llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst
llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst
llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
llvm/docs/AMDGPU/gfx10_hwreg.rst
llvm/docs/AMDGPU/gfx10_msg.rst
llvm/docs/AMDGPU/gfx10_tgt.rst
llvm/docs/AMDGPU/gfx10_waitcnt.rst
Removed:
llvm/docs/AMDGPU/gfx10_imm16.rst
llvm/docs/AMDGPU/gfx10_imm16_1.rst
llvm/docs/AMDGPU/gfx10_imm16_2.rst
llvm/docs/AMDGPU/gfx10_m.rst
llvm/docs/AMDGPU/gfx10_m_1.rst
llvm/docs/AMDGPU/gfx10_saddr.rst
llvm/docs/AMDGPU/gfx10_saddr_1.rst
llvm/docs/AMDGPU/gfx10_sbase.rst
llvm/docs/AMDGPU/gfx10_sbase_1.rst
llvm/docs/AMDGPU/gfx10_sbase_2.rst
llvm/docs/AMDGPU/gfx10_sdata.rst
llvm/docs/AMDGPU/gfx10_sdata_1.rst
llvm/docs/AMDGPU/gfx10_sdata_2.rst
llvm/docs/AMDGPU/gfx10_sdata_3.rst
llvm/docs/AMDGPU/gfx10_sdata_4.rst
llvm/docs/AMDGPU/gfx10_sdata_5.rst
llvm/docs/AMDGPU/gfx10_sdst.rst
llvm/docs/AMDGPU/gfx10_sdst_1.rst
llvm/docs/AMDGPU/gfx10_sdst_2.rst
llvm/docs/AMDGPU/gfx10_sdst_3.rst
llvm/docs/AMDGPU/gfx10_sdst_4.rst
llvm/docs/AMDGPU/gfx10_sdst_5.rst
llvm/docs/AMDGPU/gfx10_sdst_6.rst
llvm/docs/AMDGPU/gfx10_sdst_7.rst
llvm/docs/AMDGPU/gfx10_sdst_8.rst
llvm/docs/AMDGPU/gfx10_simm32.rst
llvm/docs/AMDGPU/gfx10_simm32_1.rst
llvm/docs/AMDGPU/gfx10_simm32_2.rst
llvm/docs/AMDGPU/gfx10_soffset.rst
llvm/docs/AMDGPU/gfx10_soffset_1.rst
llvm/docs/AMDGPU/gfx10_soffset_2.rst
llvm/docs/AMDGPU/gfx10_src.rst
llvm/docs/AMDGPU/gfx10_src_1.rst
llvm/docs/AMDGPU/gfx10_src_2.rst
llvm/docs/AMDGPU/gfx10_src_3.rst
llvm/docs/AMDGPU/gfx10_src_4.rst
llvm/docs/AMDGPU/gfx10_src_5.rst
llvm/docs/AMDGPU/gfx10_src_6.rst
llvm/docs/AMDGPU/gfx10_src_7.rst
llvm/docs/AMDGPU/gfx10_src_8.rst
llvm/docs/AMDGPU/gfx10_srsrc.rst
llvm/docs/AMDGPU/gfx10_srsrc_1.rst
llvm/docs/AMDGPU/gfx10_ssrc.rst
llvm/docs/AMDGPU/gfx10_ssrc_1.rst
llvm/docs/AMDGPU/gfx10_ssrc_2.rst
llvm/docs/AMDGPU/gfx10_ssrc_3.rst
llvm/docs/AMDGPU/gfx10_ssrc_4.rst
llvm/docs/AMDGPU/gfx10_ssrc_5.rst
llvm/docs/AMDGPU/gfx10_ssrc_6.rst
llvm/docs/AMDGPU/gfx10_ssrc_7.rst
llvm/docs/AMDGPU/gfx10_ssrc_8.rst
llvm/docs/AMDGPU/gfx10_vaddr.rst
llvm/docs/AMDGPU/gfx10_vaddr_1.rst
llvm/docs/AMDGPU/gfx10_vaddr_2.rst
llvm/docs/AMDGPU/gfx10_vaddr_3.rst
llvm/docs/AMDGPU/gfx10_vaddr_4.rst
llvm/docs/AMDGPU/gfx10_vaddr_5.rst
llvm/docs/AMDGPU/gfx10_vdata.rst
llvm/docs/AMDGPU/gfx10_vdata0.rst
llvm/docs/AMDGPU/gfx10_vdata0_1.rst
llvm/docs/AMDGPU/gfx10_vdata1.rst
llvm/docs/AMDGPU/gfx10_vdata1_1.rst
llvm/docs/AMDGPU/gfx10_vdata_1.rst
llvm/docs/AMDGPU/gfx10_vdata_10.rst
llvm/docs/AMDGPU/gfx10_vdata_2.rst
llvm/docs/AMDGPU/gfx10_vdata_3.rst
llvm/docs/AMDGPU/gfx10_vdata_4.rst
llvm/docs/AMDGPU/gfx10_vdata_5.rst
llvm/docs/AMDGPU/gfx10_vdata_6.rst
llvm/docs/AMDGPU/gfx10_vdata_7.rst
llvm/docs/AMDGPU/gfx10_vdata_8.rst
llvm/docs/AMDGPU/gfx10_vdata_9.rst
llvm/docs/AMDGPU/gfx10_vdst.rst
llvm/docs/AMDGPU/gfx10_vdst_1.rst
llvm/docs/AMDGPU/gfx10_vdst_10.rst
llvm/docs/AMDGPU/gfx10_vdst_11.rst
llvm/docs/AMDGPU/gfx10_vdst_12.rst
llvm/docs/AMDGPU/gfx10_vdst_13.rst
llvm/docs/AMDGPU/gfx10_vdst_2.rst
llvm/docs/AMDGPU/gfx10_vdst_3.rst
llvm/docs/AMDGPU/gfx10_vdst_4.rst
llvm/docs/AMDGPU/gfx10_vdst_5.rst
llvm/docs/AMDGPU/gfx10_vdst_6.rst
llvm/docs/AMDGPU/gfx10_vdst_7.rst
llvm/docs/AMDGPU/gfx10_vdst_8.rst
llvm/docs/AMDGPU/gfx10_vdst_9.rst
llvm/docs/AMDGPU/gfx10_vsrc.rst
llvm/docs/AMDGPU/gfx10_vsrc_1.rst
llvm/docs/AMDGPU/gfx10_vsrc_2.rst
llvm/docs/AMDGPU/gfx10_vsrc_3.rst
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
index e4207084ee239..ec7ff6da472e8 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
@@ -32,1263 +32,1265 @@ Instructions
DPP16
------------------------
+-----
.. parsed-literal::
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
- v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
DPP8
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
- v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
DS
------------------------
+--
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_append :ref:`vdst<amdgpu_synid_gfx10_vdst>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>`
- ds_cmpst_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_consume :ref:`vdst<amdgpu_synid_gfx10_vdst>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_init :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_p :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_release_all :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_v :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_nop
- ds_or_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_ordered_count :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>`
- ds_read2_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_read2st64_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_addtid_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b128 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_b96 :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_rsub_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_sub_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_swizzle_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_write2st64_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_addtid_b32 :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b128 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_2>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b16 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b8 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_b96 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_3>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_write_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_ordered_count :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_addtid_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid_gfx10_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_addtid_b32 :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx10_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx10_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
EXP
------------------------
+---
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- exp :ref:`tgt<amdgpu_synid_gfx10_tgt>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_1>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_1>`, :ref:`vsrc3<amdgpu_synid_gfx10_vsrc_1>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+ exp :ref:`tgt<amdgpu_synid_gfx10_tgt>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_533a4e>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_533a4e>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_533a4e>`, :ref:`vsrc3<amdgpu_synid_gfx10_vsrc_533a4e>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
FLAT
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- flat_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- flat_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_byte :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_dword :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_3>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_2>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_short :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- global_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_byte :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_dword :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_short :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- global_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_byte :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_dword :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_short :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_and :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_or :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid_gfx10_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx10_vdst_463513>`::ref:`opt<amdgpu_synid_gfx10_opt>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_byte :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dword :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_short :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dword :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
MIMG
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- image_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_5>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_5>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_gather4 :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_gather4_o :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_get_lod :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
- image_get_resinfo :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
- image_load :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_load_mip_pck :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
- image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
- image_load_pck :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
- image_load_pck_sgn :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
- image_sample :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cd_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_d_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_l :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_c_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cd_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_d_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_l :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_sample_o :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_store :ref:`vdata<amdgpu_synid_gfx10_vdata_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip :ref:`vdata<amdgpu_synid_gfx10_vdata_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
- image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx10_vdata_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
- image_store_pck :ref:`vdata<amdgpu_synid_gfx10_vdata_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_gather4 :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_o :ref:`vdst<amdgpu_synid_gfx10_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_get_lod :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid_gfx10_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_sample :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_o_g16 :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_o :ref:`vdst<amdgpu_synid_gfx10_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store :ref:`vdata<amdgpu_synid_gfx10_vdata_15d255>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip :ref:`vdata<amdgpu_synid_gfx10_vdata_15d255>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx10_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_store_pck :ref:`vdata<amdgpu_synid_gfx10_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
MTBUF
------------------------
+-----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
MUBUF
------------------------
+-----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_10>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_10>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx10_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx10_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_gl0_inv
buffer_gl1_inv
- buffer_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
- buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
- buffer_store_byte :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dword :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
- buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dword :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx10_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx10_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx10_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx10_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx10_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx10_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx10_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx10_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx10_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx10_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_b556e6>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
SDWA
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_class_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_eq_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_f_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ge_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_gt_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_le_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lg_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_lt_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ne_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_neq_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nge_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_ngt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nle_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlg_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_nlt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_o_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_t_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_tru_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cmpx_u_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_cos_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cos_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_exp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_floor_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_fract_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_log_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_log_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_max_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_min_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_movreld_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_movrels_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_movrelsd_2_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_movrelsd_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_mul_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_not_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_or_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sin_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sin_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_sub_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_sub_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_subrev_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
- v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
- v_xor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f16_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f32_sdwa :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cos_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_e0345d>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_log_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movreld_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movrels_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movrelsd_2_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movrelsd_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mul_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_not_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_or_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sub_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx10_src_37d670>`::ref:`m<amdgpu_synid_gfx10_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
SMEM
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_atc_probe :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`
- s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`
- s_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_2>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_2>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_4>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_5>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
- s_dcache_discard :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`
- s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`
+ s_atc_probe :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>`
+ s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx10_probe>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>`
+ s_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_c6aec1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx10_sdata_3d2ab7>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx10_sdata_7e874d>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>`
s_dcache_inv
s_dcache_wb
- s_get_waveid_in_workgroup :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`
+ s_get_waveid_in_workgroup :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`
s_gl1_inv
- s_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_4>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_5>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_memrealtime :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
- s_memtime :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
- s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_4>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
- s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
- s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx10_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx10_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_memrealtime :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
+ s_memtime :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx10_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_b2d796>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid_gfx10_sdata_6fbc49>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx10_sdata_81ba27>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx10_sdata_7cbd60>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx10_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>`
SOP1
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_abs_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_and_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_andn1_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_andn1_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_andn2_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_andn2_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- s_brev_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_brev_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_ff0_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_ff0_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_ff1_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_ff1_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_flbit_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_flbit_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_flbit_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_flbit_i32_i64 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`
- s_mov_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_mov_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2>`
- s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
- s_movrelsd_2_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2>`
- s_nand_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_nor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_not_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_not_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_or_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_or_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_orn1_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_orn2_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_quadmask_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_quadmask_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_rfe_b64 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
- s_setpc_b64 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
- s_sext_i32_i16 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_sext_i32_i8 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_swappc_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
- s_wqm_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_wqm_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_xnor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
- s_xor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
- s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
+ s_abs_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_and_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_andn1_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_andn1_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_andn2_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_andn2_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_6fbc49>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_81ba27>`
+ s_movrelsd_2_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_6fbc49>`
+ s_nand_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_nor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_not_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_not_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_or_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_orn1_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_orn2_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_81ba27>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_81ba27>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_81ba27>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_xnor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_xor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2a042f>`
SOP2
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_abs
diff _i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_add_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_addc_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_and_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_and_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_andn2_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_andn2_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_ashr_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_ashr_i64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_bfe_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_bfe_i64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_bfe_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_bfe_u64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_bfm_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_bfm_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- s_cselect_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cselect_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_lshl1_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_lshl2_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_lshl3_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_lshl4_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_lshl_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_lshl_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_lshr_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_lshr_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_max_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_max_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_min_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_min_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_mul_hi_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_mul_hi_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_mul_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_nand_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_nand_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_nor_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_nor_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_or_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_or_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_orn2_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_orn2_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_sub_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_sub_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_subb_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_xnor_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_xnor_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_xor_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_xor_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
+ s_abs
diff _i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_add_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_and_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_and_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_max_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_max_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_min_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_min_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_or_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_or_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
SOPC
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
- s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
- s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_2a042f>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7da351>`
SOPK
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- s_addk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_call_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`, :ref:`label<amdgpu_synid_gfx10_label>`
- s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
- s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
- s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
- s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
- s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
- s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
- s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`
- s_movk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`imm16<amdgpu_synid_gfx10_imm16>`
- s_setreg_b32 :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`
- s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`, :ref:`simm32<amdgpu_synid_gfx10_simm32>`
- s_subvector_loop_begin :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`label<amdgpu_synid_gfx10_label>`
- s_subvector_loop_end :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`, :ref:`label<amdgpu_synid_gfx10_label>`
- s_version :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_waitcnt_expcnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_waitcnt_lgkmcnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_waitcnt_vmcnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_waitcnt_vscnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_call_b64 :ref:`sdst<amdgpu_synid_gfx10_sdst_ea3f10>`, :ref:`label<amdgpu_synid_gfx10_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_a04fb3>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_a04fb3>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_a04fb3>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_a04fb3>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_a04fb3>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_a04fb3>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`, :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_a3e80c>`
+ s_subvector_loop_begin :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`label<amdgpu_synid_gfx10_label>`
+ s_subvector_loop_end :ref:`sdst<amdgpu_synid_gfx10_sdst_8078f5>`, :ref:`label<amdgpu_synid_gfx10_label>`
+ s_version :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_waitcnt_expcnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_waitcnt_lgkmcnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_waitcnt_vmcnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_waitcnt_vscnt :ref:`ssrc<amdgpu_synid_gfx10_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
SOPP
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **SRC**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_barrier
s_branch :ref:`label<amdgpu_synid_gfx10_label>`
s_cbranch_cdbgsys :ref:`label<amdgpu_synid_gfx10_label>`
@@ -1301,848 +1303,850 @@ SOPP
s_cbranch_scc1 :ref:`label<amdgpu_synid_gfx10_label>`
s_cbranch_vccnz :ref:`label<amdgpu_synid_gfx10_label>`
s_cbranch_vccz :ref:`label<amdgpu_synid_gfx10_label>`
- s_clause :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
+ s_clause :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
s_code_end
- s_decperflevel :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_denorm_mode :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
+ s_decperflevel :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_denorm_mode :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
s_endpgm
s_endpgm_ordered_ps_done
s_endpgm_saved
s_icache_inv
- s_incperflevel :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_inst_prefetch :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_nop :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_round_mode :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
+ s_incperflevel :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_inst_prefetch :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_nop :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_round_mode :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
s_sendmsg :ref:`msg<amdgpu_synid_gfx10_msg>`
s_sendmsghalt :ref:`msg<amdgpu_synid_gfx10_msg>`
- s_sethalt :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_setkill :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_setprio :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_sleep :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
- s_trap :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
+ s_sethalt :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_setkill :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_setprio :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_sleep :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_trap :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
s_ttracedata
- s_ttracedata_imm :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
+ s_ttracedata_imm :ref:`imm16<amdgpu_synid_gfx10_imm16_73139a>`
+ s_wait_idle
s_waitcnt :ref:`waitcnt<amdgpu_synid_gfx10_waitcnt>`
+ s_waitcnt_depctr :ref:`waitcnt_depctr<amdgpu_synid_gfx10_waitcnt_depctr>`
s_wakeup
VINTRP
------------------------
+------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_interp_mov_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`param<amdgpu_synid_gfx10_param>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_interp_p1_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_interp_p2_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_interp_mov_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`param<amdgpu_synid_gfx10_param>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_interp_p1_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_interp_p2_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
VOP1
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
v_clrexcp
- v_cos_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cos_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_4>`
- v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_4>`
- v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_exp_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_exp_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_floor_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_floor_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_floor_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_fract_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_fract_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_fract_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_log_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_log_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_mov_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_movreld_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_movrels_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
- v_movrelsd_2_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
- v_movrelsd_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
+ v_cos_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_e9e6db>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_e9e6db>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_log_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_log_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_movreld_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_movrels_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_movrelsd_2_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_movrelsd_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
v_nop
- v_not_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
+ v_not_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
v_pipeflush
- v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_readfirstlane_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8>`, :ref:`src<amdgpu_synid_gfx10_src_5>`
- v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_sin_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_sin_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
- v_swap_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
- v_swaprel_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
- v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`
+ v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_2e4c2a>`, :ref:`src<amdgpu_synid_gfx10_src_516946>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_swaprel_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`
VOP2
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
- v_add_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_add_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_add_nc_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_and_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
- v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
- v_fmaak_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_1>`
- v_fmaak_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`
- v_fmac_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_fmamk_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_7>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_1>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`
- v_fmamk_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_7>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`
- v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>`
- v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mac_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mac_legacy_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_madak_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_7>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`
- v_madmk_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_7>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`
- v_max_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_max_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_max_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_max_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_min_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_min_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_min_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_min_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mul_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mul_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_or_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_sub_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
- v_sub_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_sub_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_sub_nc_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_subrev_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
- v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_subrev_nc_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_xor_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
+ v_add_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
+ v_add_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_add_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_add_nc_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_and_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
+ v_fmaak_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_be0c1c>`
+ v_fmaak_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_6f0844>`
+ v_fmac_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_fmamk_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_be0c1c>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_fmamk_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_6f0844>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mac_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mac_legacy_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_madak_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_6f0844>`
+ v_madmk_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`simm32<amdgpu_synid_gfx10_simm32_6f0844>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_max_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_max_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_max_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_max_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_min_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_min_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_min_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_min_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_or_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_sub_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_sub_nc_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_subrev_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_subrev_nc_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
VOP3
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_add3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_add_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_add_nc_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_nc_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`clamp<amdgpu_synid_clamp>`
- v_add_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_8>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
- v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_8>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
- v_and_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ceil_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ceil_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_add_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_3ec588>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_add_nc_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_c27036>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_clrexcp_e64
- v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_class_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmpx_class_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmpx_class_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmpx_eq_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_eq_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_eq_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_eq_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_eq_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_eq_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_eq_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_f_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_f_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_f_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_f_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_f_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_ge_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ge_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_ge_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_ge_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_ge_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_ge_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_ge_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_gt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_gt_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_gt_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_gt_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_gt_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_gt_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_gt_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_le_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_le_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_le_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_le_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_le_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_le_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_le_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_lg_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lg_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lg_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_lt_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_lt_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_lt_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_lt_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_lt_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_lt_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_ne_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_ne_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_ne_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_ne_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_cmpx_ne_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_ne_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_neq_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_neq_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_neq_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nge_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_ngt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nle_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlg_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_nlt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_o_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_t_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_t_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_t_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_cmpx_t_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_cmpx_tru_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_tru_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_tru_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cmpx_u_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>`
- v_cos_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cos_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_4>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
- v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`
- v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
- v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
- v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
- v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
- v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`
- v_exp_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_exp_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_floor_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_floor_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_floor_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fma_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fmac_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_fract_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
- v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
- v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`
- v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_mov_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`param<amdgpu_synid_gfx10_param>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16x2<amdgpu_synid_gfx10_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_interp_p2_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
- v_interp_p2_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_log_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_log_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`
- v_mac_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mac_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i32_i24 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_i64_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_legacy_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mad_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u32_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u32_u24 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mad_u64_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max3_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_max3_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max3_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_max3_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_max3_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_max3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_max_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_max_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_max_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_max_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_max_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_med3_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_med3_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_med3_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_med3_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_med3_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_med3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_min3_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_min3_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min3_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_min3_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_min3_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_min3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_min_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_min_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_min_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_min_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_min_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mov_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_movreld_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_movrels_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
- v_movrelsd_2_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
- v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
- v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`u32x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_2>`::ref:`u32x4<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_msad_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`
- v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_mullit_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmpx_class_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmpx_class_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmpx_eq_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_eq_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_eq_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_eq_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_eq_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_eq_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_f_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_f_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_f_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_f_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_ge_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_ge_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_ge_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_ge_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_ge_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_ge_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_gt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_gt_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_gt_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_gt_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_gt_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_gt_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_le_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_le_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_le_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_le_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_le_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_le_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_lg_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_lt_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_lt_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_lt_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_lt_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_lt_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_ne_i16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_ne_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_ne_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_ne_u16_e64 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_cmpx_ne_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_ne_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_neq_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_t_i32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_t_i64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_t_u32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_cmpx_t_u64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_cmpx_tru_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f64_e64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_3ec588>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_e9e6db>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_e9e6db>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
+ v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_mov_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`param<amdgpu_synid_gfx10_param>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f16x2<amdgpu_synid_gfx10_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p2_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_interp_p2_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_c27036>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_c27036>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mac_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_max_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_min_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_movreld_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_movrels_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_movrelsd_2_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_69a144>`::ref:`u32x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_e016a1>`::ref:`u32x4<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mullit_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
v_nop_e64
- v_not_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_or3_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_or_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
- v_perm_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_permlane16_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_6>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_6>` :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
- v_permlanex16_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_6>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_6>` :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_permlane16_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_9a4448>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_9a4448>` :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
+ v_permlanex16_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vdata<amdgpu_synid_gfx10_vdata_6802ce>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_9a4448>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_9a4448>` :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
v_pipeflush_e64
- v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_rcp_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_readlane_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_8>`, :ref:`src0<amdgpu_synid_gfx10_src_5>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7>`
- v_rndne_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rndne_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_rsq_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sad_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
- v_sin_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sin_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_sub_nc_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_nc_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`clamp<amdgpu_synid_clamp>`
- v_sub_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`sdst<amdgpu_synid_gfx10_sdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_subrev_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_subrev_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_6>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`clamp<amdgpu_synid_clamp>`
- v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_trunc_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`, :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
- v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_8>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7>`
- v_xad_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
- v_xor3_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`
- v_xor_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_d5cd94>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid_gfx10_sdst_2e4c2a>`, :ref:`src0<amdgpu_synid_gfx10_src_516946>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_48e8e7>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_3ec588>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_nc_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_i32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_3ec588>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx10_src_d5cd94>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_054e2a>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_48e8e7>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
+ v_xor3_b32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`
VOP3P
------------------------
+-----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_add_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_fma_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>`, :ref:`src2<amdgpu_synid_gfx10_src_6>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mad_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mad_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`, :ref:`src2<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_max_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_max_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_min_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_min_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_mul_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`src1<amdgpu_synid_gfx10_src_6>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
- v_pk_sub_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
- v_pk_sub_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`src1<amdgpu_synid_gfx10_src_8>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>`::ref:`m<amdgpu_synid_gfx10_m_f5d306>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_c27036>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx10_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_c27036>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_c27036>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>`, :ref:`src2<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`src1<amdgpu_synid_gfx10_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx10_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
VOPC
------------------------
+----
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_class_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmpx_class_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmpx_class_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
- v_cmpx_eq_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_eq_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_eq_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_eq_i16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_eq_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_eq_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_eq_u16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_eq_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_eq_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_f_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_f_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_f_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_f_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_f_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_f_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_f_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_ge_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ge_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ge_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_ge_i16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ge_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ge_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_ge_u16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ge_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ge_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_gt_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_gt_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_gt_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_gt_i16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_gt_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_gt_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_gt_u16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_gt_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_gt_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_le_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_le_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_le_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_le_i16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_le_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_le_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_le_u16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_le_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_le_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_lg_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lg_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lg_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_lt_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lt_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lt_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_lt_i16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lt_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lt_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_lt_u16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lt_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_lt_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_ne_i16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ne_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ne_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_ne_u16 :ref:`src0<amdgpu_synid_gfx10_src_4>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ne_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ne_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_neq_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_neq_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_neq_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_nge_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nge_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nge_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_ngt_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ngt_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_ngt_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_nle_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nle_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nle_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_nlg_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nlg_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nlg_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_nlt_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nlt_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_nlt_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_o_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_o_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_o_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_t_i32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_t_i64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_t_u32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_t_u64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_tru_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_tru_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_tru_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
- v_cmpx_u_f16 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_u_f32 :ref:`src0<amdgpu_synid_gfx10_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
- v_cmpx_u_f64 :ref:`src0<amdgpu_synid_gfx10_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_class_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmpx_class_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmpx_class_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
+ v_cmpx_eq_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_eq_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_eq_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_eq_i16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_eq_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_eq_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_eq_u16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_eq_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_eq_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_f_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_f_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_f_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_f_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_f_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_f_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_f_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_ge_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ge_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ge_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_ge_i16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ge_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ge_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_ge_u16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ge_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ge_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_gt_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_gt_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_gt_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_gt_i16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_gt_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_gt_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_gt_u16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_gt_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_gt_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_le_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_le_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_le_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_le_i16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_le_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_le_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_le_u16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_le_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_le_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_lg_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lg_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lg_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_lt_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lt_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lt_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_lt_i16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lt_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lt_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_lt_u16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lt_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_lt_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_ne_i16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ne_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ne_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_ne_u16 :ref:`src0<amdgpu_synid_gfx10_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ne_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ne_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_neq_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_neq_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_neq_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_nge_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nge_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nge_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_ngt_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ngt_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_ngt_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_nle_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nle_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nle_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_nlg_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nlg_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nlg_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_nlt_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nlt_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_nlt_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_o_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_o_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_o_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_t_i32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_t_i64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_t_u32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_t_u64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_tru_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_tru_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_tru_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
+ v_cmpx_u_f16 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_u_f32 :ref:`src0<amdgpu_synid_gfx10_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_6802ce>`
+ v_cmpx_u_f64 :ref:`src0<amdgpu_synid_gfx10_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_fd235e>`
.. |---| unicode:: U+02014 .. em dash
@@ -2153,103 +2157,102 @@ VOPC
gfx10_dst
gfx10_fx_operand
gfx10_hwreg
- gfx10_imm16
- gfx10_imm16_1
- gfx10_imm16_2
+ gfx10_imm16_73139a
+ gfx10_imm16_a04fb3
gfx10_label
- gfx10_m
- gfx10_m_1
+ gfx10_m_254bcb
+ gfx10_m_f5d306
gfx10_msg
gfx10_opt
gfx10_param
gfx10_probe
- gfx10_saddr
- gfx10_saddr_1
- gfx10_sbase
- gfx10_sbase_1
- gfx10_sbase_2
- gfx10_sdata
- gfx10_sdata_1
- gfx10_sdata_2
- gfx10_sdata_3
- gfx10_sdata_4
- gfx10_sdata_5
- gfx10_sdst
- gfx10_sdst_1
- gfx10_sdst_2
- gfx10_sdst_3
- gfx10_sdst_4
- gfx10_sdst_5
- gfx10_sdst_6
- gfx10_sdst_7
- gfx10_sdst_8
- gfx10_simm32
- gfx10_simm32_1
- gfx10_simm32_2
- gfx10_soffset
- gfx10_soffset_1
- gfx10_soffset_2
- gfx10_src
- gfx10_src_1
- gfx10_src_2
- gfx10_src_3
- gfx10_src_4
- gfx10_src_5
- gfx10_src_6
- gfx10_src_7
- gfx10_src_8
- gfx10_srsrc
- gfx10_srsrc_1
+ gfx10_saddr_beaa25
+ gfx10_saddr_da2a8a
+ gfx10_sbase_010ce0
+ gfx10_sbase_020892
+ gfx10_sbase_b2d796
+ gfx10_sdata_3d2ab7
+ gfx10_sdata_6fbc49
+ gfx10_sdata_7cbd60
+ gfx10_sdata_7e874d
+ gfx10_sdata_81ba27
+ gfx10_sdata_c6aec1
+ gfx10_sdst_0804b1
+ gfx10_sdst_2e4c2a
+ gfx10_sdst_362c37
+ gfx10_sdst_3759f6
+ gfx10_sdst_386c33
+ gfx10_sdst_3bc700
+ gfx10_sdst_54e16e
+ gfx10_sdst_8078f5
+ gfx10_sdst_ea3f10
+ gfx10_simm32_6f0844
+ gfx10_simm32_a3e80c
+ gfx10_simm32_be0c1c
+ gfx10_soffset_59fade
+ gfx10_soffset_b556e6
+ gfx10_soffset_c40a5a
+ gfx10_src_37d670
+ gfx10_src_516946
+ gfx10_src_823582
+ gfx10_src_c27036
+ gfx10_src_cf1cda
+ gfx10_src_d5cd94
+ gfx10_src_e0345d
+ gfx10_src_e9e6db
+ gfx10_srsrc_cf7132
+ gfx10_srsrc_e73d16
gfx10_ssamp
- gfx10_ssrc
- gfx10_ssrc_1
- gfx10_ssrc_2
- gfx10_ssrc_3
- gfx10_ssrc_4
- gfx10_ssrc_5
- gfx10_ssrc_6
- gfx10_ssrc_7
- gfx10_ssrc_8
+ gfx10_ssrc_054e2a
+ gfx10_ssrc_2a042f
+ gfx10_ssrc_3ec588
+ gfx10_ssrc_460c63
+ gfx10_ssrc_48e8e7
+ gfx10_ssrc_6fbc49
+ gfx10_ssrc_7da351
+ gfx10_ssrc_81ba27
+ gfx10_ssrc_9a4448
gfx10_tgt
gfx10_type_deviation
- gfx10_vaddr
- gfx10_vaddr_1
- gfx10_vaddr_2
- gfx10_vaddr_3
- gfx10_vaddr_4
- gfx10_vaddr_5
+ gfx10_vaddr_76b997
+ gfx10_vaddr_9aeece
+ gfx10_vaddr_9f7133
+ gfx10_vaddr_b73dc0
+ gfx10_vaddr_cdc744
+ gfx10_vaddr_f20ee4
gfx10_vcc
- gfx10_vdata
- gfx10_vdata0
- gfx10_vdata0_1
- gfx10_vdata1
- gfx10_vdata1_1
- gfx10_vdata_1
- gfx10_vdata_10
- gfx10_vdata_2
- gfx10_vdata_3
- gfx10_vdata_4
- gfx10_vdata_5
- gfx10_vdata_6
- gfx10_vdata_7
- gfx10_vdata_8
- gfx10_vdata_9
- gfx10_vdst
- gfx10_vdst_1
- gfx10_vdst_10
- gfx10_vdst_11
- gfx10_vdst_12
- gfx10_vdst_13
- gfx10_vdst_2
- gfx10_vdst_3
- gfx10_vdst_4
- gfx10_vdst_5
- gfx10_vdst_6
- gfx10_vdst_7
- gfx10_vdst_8
- gfx10_vdst_9
- gfx10_vsrc
- gfx10_vsrc_1
- gfx10_vsrc_2
- gfx10_vsrc_3
+ gfx10_vdata0_6802ce
+ gfx10_vdata0_fd235e
+ gfx10_vdata1_6802ce
+ gfx10_vdata1_fd235e
+ gfx10_vdata_15d255
+ gfx10_vdata_325b78
+ gfx10_vdata_4d8ecf
+ gfx10_vdata_56f215
+ gfx10_vdata_6802ce
+ gfx10_vdata_87fb90
+ gfx10_vdata_b2a787
+ gfx10_vdata_c08393
+ gfx10_vdata_c61803
+ gfx10_vdata_e016a1
+ gfx10_vdata_fd235e
+ gfx10_vdst_3d7dcf
+ gfx10_vdst_463513
+ gfx10_vdst_473a69
+ gfx10_vdst_48d3a8
+ gfx10_vdst_48e42f
+ gfx10_vdst_5d50a1
+ gfx10_vdst_69a144
+ gfx10_vdst_719833
+ gfx10_vdst_89680f
+ gfx10_vdst_a49b76
+ gfx10_vdst_bdb32f
+ gfx10_vdst_d0dc43
+ gfx10_vdst_d7c57e
+ gfx10_vdst_f47754
+ gfx10_vsrc_533a4e
+ gfx10_vsrc_6802ce
+ gfx10_vsrc_e016a1
+ gfx10_vsrc_fd235e
gfx10_waitcnt
+ gfx10_waitcnt_depctr
diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst
index 16b5990dadbe9..c7c821ab2fff8 100644
--- a/llvm/docs/AMDGPU/gfx10_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst
@@ -41,27 +41,27 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
Defined register *names* include:
- =================== ==========================================
- Name Description
- =================== ==========================================
- HW_REG_MODE Shader writeable mode bits.
- HW_REG_STATUS Shader read-only status.
- HW_REG_TRAPSTS Trap status.
- HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
- HW_REG_HW_ID2 Id of queue, pipeline, etc.
- HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
- HW_REG_LDS_ALLOC Per-wave LDS allocation.
- HW_REG_IB_STS Counters of outstanding instructions.
- HW_REG_SH_MEM_BASES Memory aperture.
- HW_REG_TBA_LO tba_lo register.
- HW_REG_TBA_HI tba_hi register.
- HW_REG_TMA_LO tma_lo register.
- HW_REG_TMA_HI tma_hi register.
- HW_REG_FLAT_SCR_LO flat_scratch_lo register.
- HW_REG_FLAT_SCR_HI flat_scratch_hi register.
- HW_REG_XNACK_MASK xnack_mask register.
- HW_REG_POPS_PACKER pops_packer register.
- =================== ==========================================
+ ==================== ==========================================
+ Name Description
+ ==================== ==========================================
+ HW_REG_MODE Shader writeable mode bits.
+ HW_REG_STATUS Shader read-only status.
+ HW_REG_TRAPSTS Trap status.
+ HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
+ HW_REG_HW_ID2 Id of queue, pipeline, etc.
+ HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
+ HW_REG_LDS_ALLOC Per-wave LDS allocation.
+ HW_REG_IB_STS Counters of outstanding instructions.
+ HW_REG_SH_MEM_BASES Memory aperture.
+ HW_REG_TBA_LO tba_lo register.
+ HW_REG_TBA_HI tba_hi register.
+ HW_REG_TMA_LO tma_lo register.
+ HW_REG_TMA_HI tma_hi register.
+ HW_REG_FLAT_SCR_LO flat_scratch_lo register.
+ HW_REG_FLAT_SCR_HI flat_scratch_hi register.
+ HW_REG_XNACK_MASK xnack_mask register.
+ HW_REG_POPS_PACKER pops_packer register.
+ ==================== ==========================================
Examples:
diff --git a/llvm/docs/AMDGPU/gfx10_imm16_2.rst b/llvm/docs/AMDGPU/gfx10_imm16_2.rst
deleted file mode 100644
index 2500954a77ed9..0000000000000
--- a/llvm/docs/AMDGPU/gfx10_imm16_2.rst
+++ /dev/null
@@ -1,13 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx10_imm16_2:
-
-imm16
-=====
-
-A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
diff --git a/llvm/docs/AMDGPU/gfx10_imm16.rst b/llvm/docs/AMDGPU/gfx10_imm16_73139a.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_imm16.rst
rename to llvm/docs/AMDGPU/gfx10_imm16_73139a.rst
index 22d73ae5eccef..085b8c7a5742f 100644
--- a/llvm/docs/AMDGPU/gfx10_imm16.rst
+++ b/llvm/docs/AMDGPU/gfx10_imm16_73139a.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_imm16:
+.. _amdgpu_synid_gfx10_imm16_73139a:
imm16
=====
diff --git a/llvm/docs/AMDGPU/gfx10_imm16_1.rst b/llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_imm16_1.rst
rename to llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst
index ee2380386d3eb..083654bf5431e 100644
--- a/llvm/docs/AMDGPU/gfx10_imm16_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_imm16_1:
+.. _amdgpu_synid_gfx10_imm16_a04fb3:
imm16
=====
diff --git a/llvm/docs/AMDGPU/gfx10_m_1.rst b/llvm/docs/AMDGPU/gfx10_m_254bcb.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_m_1.rst
rename to llvm/docs/AMDGPU/gfx10_m_254bcb.rst
index b3f9d2f22e93b..134854f0e8c3a 100644
--- a/llvm/docs/AMDGPU/gfx10_m_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_m_254bcb.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_m_1:
+.. _amdgpu_synid_gfx10_m_254bcb:
m
=
diff --git a/llvm/docs/AMDGPU/gfx10_m.rst b/llvm/docs/AMDGPU/gfx10_m_f5d306.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_m.rst
rename to llvm/docs/AMDGPU/gfx10_m_f5d306.rst
index 8d4480bcf589a..bfef084373c70 100644
--- a/llvm/docs/AMDGPU/gfx10_m.rst
+++ b/llvm/docs/AMDGPU/gfx10_m_f5d306.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_m:
+.. _amdgpu_synid_gfx10_m_f5d306:
m
=
diff --git a/llvm/docs/AMDGPU/gfx10_msg.rst b/llvm/docs/AMDGPU/gfx10_msg.rst
index 2ebd4f00cdf88..d72f53580b2f8 100644
--- a/llvm/docs/AMDGPU/gfx10_msg.rst
+++ b/llvm/docs/AMDGPU/gfx10_msg.rst
@@ -47,29 +47,28 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
Each message type supports specific operations:
- =================== ========== ============================== ============ ==========
- Message name Message Id Supported Operations Operation Id Stream Id
- =================== ========== ============================== ============ ==========
- MSG_INTERRUPT 1 \- \- \-
- MSG_GS 2 GS_OP_CUT 1 Optional
- \ GS_OP_EMIT 2 Optional
- \ GS_OP_EMIT_CUT 3 Optional
- MSG_GS_DONE 3 GS_OP_NOP 0 \-
- \ GS_OP_CUT 1 Optional
- \ GS_OP_EMIT 2 Optional
- \ GS_OP_EMIT_CUT 3 Optional
- MSG_SAVEWAVE 4 \- \- \-
- MSG_STALL_WAVE_GEN 5 \- \- \-
- MSG_HALT_WAVES 6 \- \- \-
- MSG_ORDERED_PS_DONE 7 \- \- \-
- MSG_GS_ALLOC_REQ 9 \- \- \-
- MSG_GET_DOORBELL 10 \- \- \-
- MSG_GET_DDID 11 \- \- \-
- MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
- \ SYSMSG_OP_REG_RD 2 \-
- \ SYSMSG_OP_HOST_TRAP_ACK 3 \-
- \ SYSMSG_OP_TTRACE_PC 4 \-
- =================== ========== ============================== ============ ==========
+ ====================== ========== ============================== ============ ==========
+ Message name Message Id Supported Operations Operation Id Stream Id
+ ====================== ========== ============================== ============ ==========
+ MSG_INTERRUPT 1 \- \- \-
+ MSG_GS 2 GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_DONE 3 GS_OP_NOP 0 \-
+ \ GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_SAVEWAVE 4 \- \- \-
+ MSG_STALL_WAVE_GEN 5 \- \- \-
+ MSG_HALT_WAVES 6 \- \- \-
+ MSG_ORDERED_PS_DONE 7 \- \- \-
+ MSG_GS_ALLOC_REQ 9 \- \- \-
+ MSG_GET_DOORBELL 10 \- \- \-
+ MSG_GET_DDID 11 \- \- \-
+ MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
+ \ SYSMSG_OP_REG_RD 2 \-
+ \ SYSMSG_OP_TTRACE_PC 4 \-
+ ====================== ========== ============================== ============ ==========
*Sendmsg* arguments are validated depending on how *type* value is specified:
diff --git a/llvm/docs/AMDGPU/gfx10_saddr.rst b/llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst
similarity index 80%
rename from llvm/docs/AMDGPU/gfx10_saddr.rst
rename to llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst
index 27d947ccfe027..7ede26f3665fb 100644
--- a/llvm/docs/AMDGPU/gfx10_saddr.rst
+++ b/llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst
@@ -5,14 +5,14 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_saddr:
+.. _amdgpu_synid_gfx10_saddr_beaa25:
saddr
=====
An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
-See :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` for description of available addressing modes.
+See :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` for description of available addressing modes.
*Size:* 2 dwords.
diff --git a/llvm/docs/AMDGPU/gfx10_saddr_1.rst b/llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst
similarity index 78%
rename from llvm/docs/AMDGPU/gfx10_saddr_1.rst
rename to llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst
index ba860500d372a..8e5e30c47311e 100644
--- a/llvm/docs/AMDGPU/gfx10_saddr_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst
@@ -5,14 +5,14 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_saddr_1:
+.. _amdgpu_synid_gfx10_saddr_da2a8a:
saddr
=====
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
-Either this operand or :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
+Either this operand or :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>` must be set to :ref:`off<amdgpu_synid_off>`.
*Size:* 1 dword.
diff --git a/llvm/docs/AMDGPU/gfx10_sbase_1.rst b/llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_sbase_1.rst
rename to llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst
index ea58778a43631..3d3f6cee89edb 100644
--- a/llvm/docs/AMDGPU/gfx10_sbase_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sbase_1:
+.. _amdgpu_synid_gfx10_sbase_010ce0:
sbase
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sbase.rst b/llvm/docs/AMDGPU/gfx10_sbase_020892.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_sbase.rst
rename to llvm/docs/AMDGPU/gfx10_sbase_020892.rst
index be764564eca47..292a3fad23000 100644
--- a/llvm/docs/AMDGPU/gfx10_sbase.rst
+++ b/llvm/docs/AMDGPU/gfx10_sbase_020892.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sbase:
+.. _amdgpu_synid_gfx10_sbase_020892:
sbase
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sbase_2.rst b/llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_sbase_2.rst
rename to llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst
index 14a9a4bc0496a..d22276370357e 100644
--- a/llvm/docs/AMDGPU/gfx10_sbase_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sbase_2:
+.. _amdgpu_synid_gfx10_sbase_b2d796:
sbase
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sdata.rst b/llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_sdata.rst
rename to llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst
index 3537824b06c79..d43311a682153 100644
--- a/llvm/docs/AMDGPU/gfx10_sdata.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdata:
+.. _amdgpu_synid_gfx10_sdata_3d2ab7:
sdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sdata_3.rst b/llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_sdata_3.rst
rename to llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst
index 38eedc59b338b..f1b0f38eaba5e 100644
--- a/llvm/docs/AMDGPU/gfx10_sdata_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdata_3:
+.. _amdgpu_synid_gfx10_sdata_6fbc49:
sdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sdata_5.rst b/llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_sdata_5.rst
rename to llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst
index 153153a2e0683..0dee8e899885c 100644
--- a/llvm/docs/AMDGPU/gfx10_sdata_5.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdata_5:
+.. _amdgpu_synid_gfx10_sdata_7cbd60:
sdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sdata_1.rst b/llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_sdata_1.rst
rename to llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst
index 96dc050386569..873e40c82a458 100644
--- a/llvm/docs/AMDGPU/gfx10_sdata_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdata_1:
+.. _amdgpu_synid_gfx10_sdata_7e874d:
sdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sdata_4.rst b/llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_sdata_4.rst
rename to llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst
index 07fb5ff687a82..8804836bff693 100644
--- a/llvm/docs/AMDGPU/gfx10_sdata_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdata_4:
+.. _amdgpu_synid_gfx10_sdata_81ba27:
sdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sdata_2.rst b/llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_sdata_2.rst
rename to llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst
index 22090af1cd38e..70a8b62f12648 100644
--- a/llvm/docs/AMDGPU/gfx10_sdata_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdata_2:
+.. _amdgpu_synid_gfx10_sdata_c6aec1:
sdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_4.rst b/llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_sdst_4.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst
index 8f3d8da00d04a..d82ffffcef68e 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_4:
+.. _amdgpu_synid_gfx10_sdst_0804b1:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_8.rst b/llvm/docs/AMDGPU/gfx10_sdst_2e4c2a.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_sdst_8.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_2e4c2a.rst
index 572446119cd84..105346851f1e5 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_8.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_2e4c2a.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_8:
+.. _amdgpu_synid_gfx10_sdst_2e4c2a:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_5.rst b/llvm/docs/AMDGPU/gfx10_sdst_362c37.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_sdst_5.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_362c37.rst
index 042ab9bd88b9b..4e471a0216698 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_5.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_362c37.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_5:
+.. _amdgpu_synid_gfx10_sdst_362c37:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst.rst b/llvm/docs/AMDGPU/gfx10_sdst_3759f6.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_sdst.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_3759f6.rst
index 18327a8646d17..4f45076cdfc34 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_3759f6.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst:
+.. _amdgpu_synid_gfx10_sdst_3759f6:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_3.rst b/llvm/docs/AMDGPU/gfx10_sdst_386c33.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_sdst_3.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_386c33.rst
index ba5378bd1100a..56bf1cd15eb77 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_386c33.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_3:
+.. _amdgpu_synid_gfx10_sdst_386c33:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_2.rst b/llvm/docs/AMDGPU/gfx10_sdst_3bc700.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_sdst_2.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_3bc700.rst
index 657e8e92581cb..d026ae29db42d 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_3bc700.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_2:
+.. _amdgpu_synid_gfx10_sdst_3bc700:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_1.rst b/llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_sdst_1.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst
index 4fab64c9a16e9..5577338f1f47e 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_1:
+.. _amdgpu_synid_gfx10_sdst_54e16e:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_6.rst b/llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_sdst_6.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst
index 80f18caf85d30..8dbce94afc2a2 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_6.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_6:
+.. _amdgpu_synid_gfx10_sdst_8078f5:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_sdst_7.rst b/llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_sdst_7.rst
rename to llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst
index 09ad3be1b8297..dc6ea8aafba90 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst_7.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_sdst_7:
+.. _amdgpu_synid_gfx10_sdst_ea3f10:
sdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_simm32_2.rst b/llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_simm32_2.rst
rename to llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst
index 24d3011fd6069..7694283c41521 100644
--- a/llvm/docs/AMDGPU/gfx10_simm32_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_simm32_2:
+.. _amdgpu_synid_gfx10_simm32_6f0844:
simm32
======
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
-The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
+The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx10_simm32.rst b/llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_simm32.rst
rename to llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst
index 44f1f517349e5..5c487018426f5 100644
--- a/llvm/docs/AMDGPU/gfx10_simm32.rst
+++ b/llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_simm32:
+.. _amdgpu_synid_gfx10_simm32_a3e80c:
simm32
======
diff --git a/llvm/docs/AMDGPU/gfx10_simm32_1.rst b/llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_simm32_1.rst
rename to llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst
index 54090bfedc8f9..70a9acbb9ee71 100644
--- a/llvm/docs/AMDGPU/gfx10_simm32_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst
@@ -5,10 +5,10 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_simm32_1:
+.. _amdgpu_synid_gfx10_simm32_be0c1c:
simm32
======
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
-The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
+The value is converted to *f16* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx10_soffset_2.rst b/llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_soffset_2.rst
rename to llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
index 772d887bf217f..1d5de435147e9 100644
--- a/llvm/docs/AMDGPU/gfx10_soffset_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_soffset_59fade.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_soffset_2:
+.. _amdgpu_synid_gfx10_soffset_59fade:
soffset
=======
diff --git a/llvm/docs/AMDGPU/gfx10_soffset.rst b/llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_soffset.rst
rename to llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst
index 0154df93ec841..d57506daede03 100644
--- a/llvm/docs/AMDGPU/gfx10_soffset.rst
+++ b/llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_soffset:
+.. _amdgpu_synid_gfx10_soffset_b556e6:
soffset
=======
diff --git a/llvm/docs/AMDGPU/gfx10_soffset_1.rst b/llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_soffset_1.rst
rename to llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
index b73e114d17d44..a3739bd6c6ed2 100644
--- a/llvm/docs/AMDGPU/gfx10_soffset_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_soffset_1:
+.. _amdgpu_synid_gfx10_soffset_c40a5a:
soffset
=======
diff --git a/llvm/docs/AMDGPU/gfx10_src.rst b/llvm/docs/AMDGPU/gfx10_src_37d670.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_src.rst
rename to llvm/docs/AMDGPU/gfx10_src_37d670.rst
index f83c11822c02b..8c10a4cd33432 100644
--- a/llvm/docs/AMDGPU/gfx10_src.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_37d670.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src:
+.. _amdgpu_synid_gfx10_src_37d670:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_src_5.rst b/llvm/docs/AMDGPU/gfx10_src_516946.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_src_5.rst
rename to llvm/docs/AMDGPU/gfx10_src_516946.rst
index 44a447193ceff..7c71f7713cc9e 100644
--- a/llvm/docs/AMDGPU/gfx10_src_5.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_516946.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src_5:
+.. _amdgpu_synid_gfx10_src_516946:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_src_7.rst b/llvm/docs/AMDGPU/gfx10_src_7.rst
deleted file mode 100644
index dffdab1714325..0000000000000
--- a/llvm/docs/AMDGPU/gfx10_src_7.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx10_src_7:
-
-src
-===
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_src_2.rst b/llvm/docs/AMDGPU/gfx10_src_823582.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_src_2.rst
rename to llvm/docs/AMDGPU/gfx10_src_823582.rst
index 9bd53ddb54126..7fd81565e6496 100644
--- a/llvm/docs/AMDGPU/gfx10_src_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_823582.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src_2:
+.. _amdgpu_synid_gfx10_src_823582:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_src_8.rst b/llvm/docs/AMDGPU/gfx10_src_c27036.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_src_8.rst
rename to llvm/docs/AMDGPU/gfx10_src_c27036.rst
index 25297cfe91bde..9873fe20266df 100644
--- a/llvm/docs/AMDGPU/gfx10_src_8.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_c27036.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src_8:
+.. _amdgpu_synid_gfx10_src_c27036:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_src_6.rst b/llvm/docs/AMDGPU/gfx10_src_cf1cda.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_src_6.rst
rename to llvm/docs/AMDGPU/gfx10_src_cf1cda.rst
index b1b49b168de73..9f8896d5247bf 100644
--- a/llvm/docs/AMDGPU/gfx10_src_6.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_cf1cda.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src_6:
+.. _amdgpu_synid_gfx10_src_cf1cda:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_src_3.rst b/llvm/docs/AMDGPU/gfx10_src_d5cd94.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_src_3.rst
rename to llvm/docs/AMDGPU/gfx10_src_d5cd94.rst
index a581d7b4c96c0..021d91086e1ed 100644
--- a/llvm/docs/AMDGPU/gfx10_src_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_d5cd94.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src_3:
+.. _amdgpu_synid_gfx10_src_d5cd94:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_src_1.rst b/llvm/docs/AMDGPU/gfx10_src_e0345d.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_src_1.rst
rename to llvm/docs/AMDGPU/gfx10_src_e0345d.rst
index 67fc1c59cf50c..9ebd1627f29b6 100644
--- a/llvm/docs/AMDGPU/gfx10_src_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_e0345d.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src_1:
+.. _amdgpu_synid_gfx10_src_e0345d:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_src_4.rst b/llvm/docs/AMDGPU/gfx10_src_e9e6db.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_src_4.rst
rename to llvm/docs/AMDGPU/gfx10_src_e9e6db.rst
index 6bbb235dcf5cf..f04f555ed7cd3 100644
--- a/llvm/docs/AMDGPU/gfx10_src_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_src_e9e6db.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_src_4:
+.. _amdgpu_synid_gfx10_src_e9e6db:
src
===
diff --git a/llvm/docs/AMDGPU/gfx10_srsrc.rst b/llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_srsrc.rst
rename to llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst
index 704c2b2165125..e9996a2962b66 100644
--- a/llvm/docs/AMDGPU/gfx10_srsrc.rst
+++ b/llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_srsrc:
+.. _amdgpu_synid_gfx10_srsrc_cf7132:
srsrc
=====
diff --git a/llvm/docs/AMDGPU/gfx10_srsrc_1.rst b/llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_srsrc_1.rst
rename to llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst
index 11546818280d9..824713d224448 100644
--- a/llvm/docs/AMDGPU/gfx10_srsrc_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_srsrc_1:
+.. _amdgpu_synid_gfx10_srsrc_e73d16:
srsrc
=====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_8.rst b/llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_ssrc_8.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst
index 48a7e71b64ef3..031ef28348982 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_8.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_8:
+.. _amdgpu_synid_gfx10_ssrc_054e2a:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_ssrc_1.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst
index 96545ffc5767d..37d63ed0a030b 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_1:
+.. _amdgpu_synid_gfx10_ssrc_2a042f:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_5.rst b/llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_ssrc_5.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst
index e36c48f38e96e..84d13edb40ac7 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_5.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_5:
+.. _amdgpu_synid_gfx10_ssrc_3ec588:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_4.rst b/llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_ssrc_4.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst
index f4aef373258bd..47c4f9fc05921 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_4:
+.. _amdgpu_synid_gfx10_ssrc_460c63:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_7.rst b/llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_ssrc_7.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst
index 3507e8373b08d..3c5f34e2a6fc2 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_7.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_7:
+.. _amdgpu_synid_gfx10_ssrc_48e8e7:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_2.rst b/llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_ssrc_2.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst
index ee31917115f87..188a89c1cda0e 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_2:
+.. _amdgpu_synid_gfx10_ssrc_6fbc49:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc.rst b/llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_ssrc.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst
index cdcb9e6b3692c..2c01786543108 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc:
+.. _amdgpu_synid_gfx10_ssrc_7da351:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_3.rst b/llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_ssrc_3.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst
index aa4ff88d059a5..c4a5e455b457c 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_3:
+.. _amdgpu_synid_gfx10_ssrc_81ba27:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_6.rst b/llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_ssrc_6.rst
rename to llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst
index 15972cf702748..fb5b471e2d61b 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc_6.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_ssrc_6:
+.. _amdgpu_synid_gfx10_ssrc_9a4448:
ssrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_tgt.rst b/llvm/docs/AMDGPU/gfx10_tgt.rst
index 342466a9863fc..a8762c493f1c5 100644
--- a/llvm/docs/AMDGPU/gfx10_tgt.rst
+++ b/llvm/docs/AMDGPU/gfx10_tgt.rst
@@ -12,13 +12,13 @@ tgt
An export target:
- ============== ===================================
- Syntax Description
- ============== ===================================
- pos{0..4} Copy vertex position 0..4.
- param{0..31} Copy vertex parameter 0..31.
- mrt{0..7} Copy pixel color to the MRTs 0..7.
- mrtz Copy pixel depth (Z) data.
- prim Copy primitive (connectivity) data.
- null Copy nothing.
- ============== ===================================
+ ================== ===================================
+ Syntax Description
+ ================== ===================================
+ pos{0..4} Copy vertex position 0..4.
+ param{0..31} Copy vertex parameter 0..31.
+ mrt{0..7} Copy pixel color to the MRTs 0..7.
+ mrtz Copy pixel depth (Z) data.
+ prim Copy primitive (connectivity) data.
+ null Copy nothing.
+ ================== ===================================
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_2.rst b/llvm/docs/AMDGPU/gfx10_vaddr_2.rst
deleted file mode 100644
index 1229618b509cd..0000000000000
--- a/llvm/docs/AMDGPU/gfx10_vaddr_2.rst
+++ /dev/null
@@ -1,20 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx10_vaddr_2:
-
-vaddr
-=====
-
-A 64-bit flat global address or a 32-bit offset depending on addressing mode:
-
-* Address = :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx10_saddr>` set to :ref:`off<amdgpu_synid_off>`.
-* Address = :ref:`saddr<amdgpu_synid_gfx10_saddr>` + :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx10_saddr>` is not :ref:`off<amdgpu_synid_off>`.
-
-*Size:* 1 or 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_3.rst b/llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst
similarity index 76%
rename from llvm/docs/AMDGPU/gfx10_vaddr_3.rst
rename to llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst
index c866483f56972..41334bb1c0234 100644
--- a/llvm/docs/AMDGPU/gfx10_vaddr_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst
@@ -5,14 +5,14 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vaddr_3:
+.. _amdgpu_synid_gfx10_vaddr_76b997:
vaddr
=====
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
-Either this operand or :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` must be set to :ref:`off<amdgpu_synid_off>`.
+Either this operand or :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` must be set to :ref:`off<amdgpu_synid_off>`.
*Size:* 1 dword.
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst b/llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst
new file mode 100644
index 0000000000000..5155f2cd1f286
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx10_vaddr_9aeece:
+
+vaddr
+=====
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` + :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` is not :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_1.rst b/llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vaddr_1.rst
rename to llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst
index aca79412fd58f..f4d1f3bff0cf2 100644
--- a/llvm/docs/AMDGPU/gfx10_vaddr_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vaddr_1:
+.. _amdgpu_synid_gfx10_vaddr_9f7133:
vaddr
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_5.rst b/llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst
similarity index 96%
rename from llvm/docs/AMDGPU/gfx10_vaddr_5.rst
rename to llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst
index c5c8f6492fa02..321a0eb414fe5 100644
--- a/llvm/docs/AMDGPU/gfx10_vaddr_5.rst
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vaddr_5:
+.. _amdgpu_synid_gfx10_vaddr_b73dc0:
vaddr
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_4.rst b/llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst
similarity index 96%
rename from llvm/docs/AMDGPU/gfx10_vaddr_4.rst
rename to llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst
index 3e6d0c8a2db06..1ae91d8e32d5b 100644
--- a/llvm/docs/AMDGPU/gfx10_vaddr_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vaddr_4:
+.. _amdgpu_synid_gfx10_vaddr_cdc744:
vaddr
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr.rst b/llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vaddr.rst
rename to llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst
index e87fd388d6928..7c4934bc775b2 100644
--- a/llvm/docs/AMDGPU/gfx10_vaddr.rst
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vaddr:
+.. _amdgpu_synid_gfx10_vaddr_f20ee4:
vaddr
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata0.rst b/llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata0.rst
rename to llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst
index f660fa6296efe..6db65c6e052f5 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata0.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata0:
+.. _amdgpu_synid_gfx10_vdata0_6802ce:
vdata0
======
diff --git a/llvm/docs/AMDGPU/gfx10_vdata0_1.rst b/llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata0_1.rst
rename to llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst
index 10741bc5f8edd..5f370ebf4a070 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata0_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata0_1:
+.. _amdgpu_synid_gfx10_vdata0_fd235e:
vdata0
======
diff --git a/llvm/docs/AMDGPU/gfx10_vdata1.rst b/llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata1.rst
rename to llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst
index a775bccfb35b1..2bcfcad4a0fbf 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata1:
+.. _amdgpu_synid_gfx10_vdata1_6802ce:
vdata1
======
diff --git a/llvm/docs/AMDGPU/gfx10_vdata1_1.rst b/llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata1_1.rst
rename to llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst
index 1834fce9d8076..7015045ae1636 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata1_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata1_1:
+.. _amdgpu_synid_gfx10_vdata1_fd235e:
vdata1
======
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_6.rst b/llvm/docs/AMDGPU/gfx10_vdata_15d255.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_vdata_6.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_15d255.rst
index af43d45069246..c925debf162d4 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_6.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_15d255.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_6:
+.. _amdgpu_synid_gfx10_vdata_15d255:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_4.rst b/llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
similarity index 96%
rename from llvm/docs/AMDGPU/gfx10_vdata_4.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
index 4d922aaf524f5..9f638b817e702 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_325b78.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_4:
+.. _amdgpu_synid_gfx10_vdata_325b78:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_5.rst b/llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
similarity index 96%
rename from llvm/docs/AMDGPU/gfx10_vdata_5.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
index f23bb6b6ab293..1d8719869ff3c 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_5.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_5:
+.. _amdgpu_synid_gfx10_vdata_4d8ecf:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_3.rst b/llvm/docs/AMDGPU/gfx10_vdata_56f215.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata_3.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_56f215.rst
index 9b710c01f1706..49083c4137567 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_56f215.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_3:
+.. _amdgpu_synid_gfx10_vdata_56f215:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata.rst b/llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst
index 38048c66d8add..18c403d0a523c 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata:
+.. _amdgpu_synid_gfx10_vdata_6802ce:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_10.rst b/llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_vdata_10.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
index 31de91bc006f1..82d8b69960604 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_10.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_10:
+.. _amdgpu_synid_gfx10_vdata_87fb90:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_9.rst b/llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_vdata_9.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
index 0f0be76806d6a..d0d533eeada63 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_9.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_9:
+.. _amdgpu_synid_gfx10_vdata_b2a787:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_7.rst b/llvm/docs/AMDGPU/gfx10_vdata_c08393.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_vdata_7.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_c08393.rst
index e157fb2b98e63..4c1ee2f5abfea 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_7.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_c08393.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_7:
+.. _amdgpu_synid_gfx10_vdata_c08393:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_8.rst b/llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_vdata_8.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
index 83cefb82b62f0..07401251683ff 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_8.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_c61803.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_8:
+.. _amdgpu_synid_gfx10_vdata_c61803:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_2.rst b/llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata_2.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst
index 3cf264bea2476..c8b2fca60e918 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_2:
+.. _amdgpu_synid_gfx10_vdata_e016a1:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdata_1.rst b/llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst
similarity index 90%
rename from llvm/docs/AMDGPU/gfx10_vdata_1.rst
rename to llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst
index 2190149b49dbe..34cad64f0f6a2 100644
--- a/llvm/docs/AMDGPU/gfx10_vdata_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdata_1:
+.. _amdgpu_synid_gfx10_vdata_fd235e:
vdata
=====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_7.rst b/llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst
similarity index 94%
rename from llvm/docs/AMDGPU/gfx10_vdst_7.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst
index 425edaed52e71..d41833cc65558 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_7.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_7:
+.. _amdgpu_synid_gfx10_vdst_3d7dcf:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_5.rst b/llvm/docs/AMDGPU/gfx10_vdst_463513.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_vdst_5.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_463513.rst
index 3aca2c1edc85a..58ddf0b019d81 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_5.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_463513.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_5:
+.. _amdgpu_synid_gfx10_vdst_463513:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_8.rst b/llvm/docs/AMDGPU/gfx10_vdst_473a69.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_vdst_8.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_473a69.rst
index 1790e061d945f..05832c35d0ef5 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_8.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_473a69.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_8:
+.. _amdgpu_synid_gfx10_vdst_473a69:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_6.rst b/llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_vdst_6.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
index c0ac63b7d5141..70f713fb926b3 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_6.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_6:
+.. _amdgpu_synid_gfx10_vdst_48d3a8:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_3.rst b/llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vdst_3.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst
index c910a331c03d6..f6dcc3eda6c35 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_3:
+.. _amdgpu_synid_gfx10_vdst_48e42f:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_9.rst b/llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_vdst_9.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
index 3d3cde2c2d6ec..c24a7b0e37387 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_9.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_9:
+.. _amdgpu_synid_gfx10_vdst_5d50a1:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_2.rst b/llvm/docs/AMDGPU/gfx10_vdst_69a144.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vdst_2.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_69a144.rst
index 31ead59c2c727..37b14bd2560de 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_69a144.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_2:
+.. _amdgpu_synid_gfx10_vdst_69a144:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_13.rst b/llvm/docs/AMDGPU/gfx10_vdst_719833.rst
similarity index 95%
rename from llvm/docs/AMDGPU/gfx10_vdst_13.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_719833.rst
index 49230f4231ce2..2264b747b4b4b 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_13.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_719833.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_13:
+.. _amdgpu_synid_gfx10_vdst_719833:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst.rst b/llvm/docs/AMDGPU/gfx10_vdst_89680f.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vdst.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_89680f.rst
index d541d96ba30f4..4dc6770fd4f54 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_89680f.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst:
+.. _amdgpu_synid_gfx10_vdst_89680f:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_11.rst b/llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_vdst_11.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
index 4b63e79402c61..1a5d7028d4838 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_11.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_11:
+.. _amdgpu_synid_gfx10_vdst_a49b76:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_1.rst b/llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vdst_1.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst
index 45ab7f51b9bc5..d34fb048940f1 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_1:
+.. _amdgpu_synid_gfx10_vdst_bdb32f:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_4.rst b/llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst
similarity index 93%
rename from llvm/docs/AMDGPU/gfx10_vdst_4.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst
index 9f906f6832484..5c9086d4b8c4e 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_4.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_4:
+.. _amdgpu_synid_gfx10_vdst_d0dc43:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_10.rst b/llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_vdst_10.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
index 063c5e3004527..3cecfb2000cf6 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_10.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_10:
+.. _amdgpu_synid_gfx10_vdst_d7c57e:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vdst_12.rst b/llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
similarity index 92%
rename from llvm/docs/AMDGPU/gfx10_vdst_12.rst
rename to llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
index 95948c1b2adfc..d80d8899af53a 100644
--- a/llvm/docs/AMDGPU/gfx10_vdst_12.rst
+++ b/llvm/docs/AMDGPU/gfx10_vdst_f47754.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vdst_12:
+.. _amdgpu_synid_gfx10_vdst_f47754:
vdst
====
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc_1.rst b/llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst
similarity index 96%
rename from llvm/docs/AMDGPU/gfx10_vsrc_1.rst
rename to llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst
index 8e6a7ba370c49..b45a620832651 100644
--- a/llvm/docs/AMDGPU/gfx10_vsrc_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vsrc_1:
+.. _amdgpu_synid_gfx10_vsrc_533a4e:
vsrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc.rst b/llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vsrc.rst
rename to llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst
index 48af0a29a717a..320b97a473f29 100644
--- a/llvm/docs/AMDGPU/gfx10_vsrc.rst
+++ b/llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vsrc:
+.. _amdgpu_synid_gfx10_vsrc_6802ce:
vsrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc_2.rst b/llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vsrc_2.rst
rename to llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst
index 67ef71bdeb7e8..1ba1856f5889b 100644
--- a/llvm/docs/AMDGPU/gfx10_vsrc_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vsrc_2:
+.. _amdgpu_synid_gfx10_vsrc_e016a1:
vsrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc_3.rst b/llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst
similarity index 91%
rename from llvm/docs/AMDGPU/gfx10_vsrc_3.rst
rename to llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst
index 5ea851bf1fe14..50b7bed717163 100644
--- a/llvm/docs/AMDGPU/gfx10_vsrc_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx10_vsrc_3:
+.. _amdgpu_synid_gfx10_vsrc_fd235e:
vsrc
====
diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt.rst b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
index 405d94ab93df4..982d3bda35bd4 100644
--- a/llvm/docs/AMDGPU/gfx10_waitcnt.rst
+++ b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
@@ -19,7 +19,7 @@ The bits of this operand have the following meaning:
========== ========= ================================================ ============
15:14 3:0 VM_CNT: vector memory operations count. 0..63
\- 6:4 EXP_CNT: export count. 0..7
- \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
+ \- 13:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..63
========== ========= ================================================ ============
This operand may be specified as one of the following:
diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst b/llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst
new file mode 100644
index 0000000000000..dd0bd8e806669
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst
@@ -0,0 +1,39 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx10_waitcnt_depctr:
+
+waitcnt_depctr
+==============
+
+Dependency counters to wait for.
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* A combination of *symbolic values* described below.
+
+ ======================== ======================== ================ =================
+ Syntax Description Valid *N* Values Default *N* Value
+ ======================== ======================== ================ =================
+ depctr_sa_sdst(<*N*>) Wait for SA_SDST <= N 0..1 1
+ depctr_va_vdst(<*N*>) Wait for VA_VDST <= N 0..15 15
+ depctr_va_sdst(<*N*>) Wait for VA_SDST <= N 0..7 7
+ depctr_va_ssrc(<*N*>) Wait for VA_SSRC <= N 0..1 1
+ depctr_va_vcc(<*N*>) Wait for VA_VCC <= N 0..1 1
+ depctr_vm_vsrc(<*N*>) Wait for VM_VSRC <= N 0..7 7
+ ======================== ======================== ================ =================
+
+ These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
+
+Examples:
+
+.. parsed-literal::
+
+ s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0)
+ s_waitcnt_depctr depctr_sa_sdst(1) & depctr_va_vdst(1)
+ s_waitcnt_depctr depctr_va_vdst(3), depctr_va_sdst(5)
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