[llvm] 7e8ff96 - AArch64/GlobalISel: Regenerate mir test checks
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 11 17:12:29 PDT 2022
Author: Matt Arsenault
Date: 2022-04-11T20:12:22-04:00
New Revision: 7e8ff962b315a2462e6b9e2804a6bfade887b310
URL: https://github.com/llvm/llvm-project/commit/7e8ff962b315a2462e6b9e2804a6bfade887b310
DIFF: https://github.com/llvm/llvm-project/commit/7e8ff962b315a2462e6b9e2804a6bfade887b310.diff
LOG: AArch64/GlobalISel: Regenerate mir test checks
Minimizes the test diffs in future changes from introduction of -NEXT.
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
index 08f478e12521b..9987e9e96e960 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
@@ -15,19 +15,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: oeq
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -54,19 +57,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ogt
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 12, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -93,19 +99,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: oge
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 10, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 10, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -132,19 +141,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: olt
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 4, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 4, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -171,19 +183,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ole
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 9, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 9, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -210,20 +225,23 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: one
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 4, %bb.2, implicit $nzcv
- ; CHECK: Bcc 12, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 4, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -250,19 +268,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ord
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 7, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 7, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -289,19 +310,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: uno
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 6, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 6, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -328,20 +352,23 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ueq
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: Bcc 6, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: Bcc 6, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -368,19 +395,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ugt
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 8, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 8, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -407,19 +437,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: uge
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 5, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 5, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -446,19 +479,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ult
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -485,19 +521,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ule
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 13, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 13, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
@@ -524,19 +563,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: une
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cmp_lhs:fpr32 = COPY $s0
- ; CHECK: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
- ; CHECK: Bcc 1, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: $s0 = COPY %cmp_lhs
- ; CHECK: RET_ReallyLR implicit $s0
- ; CHECK: bb.2:
- ; CHECK: $s1 = COPY %cmp_rhs
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
+ ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
+ ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $s0 = COPY %cmp_lhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $s1 = COPY %cmp_rhs
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
index 93b0b95e4eb9e..dcf3c94058c0c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
@@ -24,18 +24,19 @@ body: |
; CHECK-LABEL: name: fcmp_more_than_one_user_no_fold
; CHECK: liveins: $s0, $s1, $w1
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
- ; CHECK: $w1 = COPY [[CSINCWr]]
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
+ ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
@@ -60,16 +61,17 @@ body: |
; CHECK-LABEL: name: fcmp_more_than_one_select
; CHECK: liveins: $s0, $s1, $w1
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
- ; CHECK: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: $s1 = COPY [[FCSELSrrr1]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: $s1 = COPY [[FCSELSrrr1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
@@ -95,13 +97,14 @@ body: |
; CHECK-LABEL: name: using_icmp
; CHECK: liveins: $s0, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:gpr(s32) = COPY $w0
%1:fpr(s32) = COPY $s0
%2:gpr(s32) = G_CONSTANT i32 0
@@ -126,13 +129,14 @@ body: |
; CHECK-LABEL: name: foeq
; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
@@ -156,19 +160,20 @@ body: |
; CHECK-LABEL: name: fueq
; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
@@ -192,19 +197,20 @@ body: |
; CHECK-LABEL: name: fone
; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
- ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
@@ -228,13 +234,14 @@ body: |
; CHECK-LABEL: name: fune
; CHECK: liveins: $s0, $s1
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
@@ -258,13 +265,14 @@ body: |
; CHECK-LABEL: name: doeq
; CHECK: liveins: $d0, $d1
- ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
- ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
- ; CHECK: $d0 = COPY [[FCSELDrrr]]
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
+ ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = COPY $d1
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
@@ -288,19 +296,20 @@ body: |
; CHECK-LABEL: name: dueq
; CHECK: liveins: $d0, $d1
- ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
- ; CHECK: $d0 = COPY [[FCSELDrrr]]
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
+ ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
+ ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = COPY $d1
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
@@ -324,19 +333,20 @@ body: |
; CHECK-LABEL: name: done
; CHECK: liveins: $d0, $d1
- ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
- ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
- ; CHECK: $d0 = COPY [[FCSELDrrr]]
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
+ ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
+ ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
+ ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = COPY $d1
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
@@ -360,13 +370,14 @@ body: |
; CHECK-LABEL: name: dune
; CHECK: liveins: $d0, $d1
- ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
- ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
- ; CHECK: $d0 = COPY [[FCSELDrrr]]
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
+ ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
+ ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = COPY $d1
%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
@@ -390,15 +401,16 @@ body: |
; CHECK-LABEL: name: copy_from_physreg
; CHECK: liveins: $s0, $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: BL @copy_from_physreg, implicit-def $w0
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
- ; CHECK: BL @copy_from_physreg, implicit-def $w0
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+ ; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
+ ; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:gpr(s32) = COPY $w0
%1:fpr(s32) = COPY $s0
%5:fpr(s32) = G_FCONSTANT float 0.000000e+00
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
index adc266c6394ea..f60be78715374 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
@@ -19,13 +19,14 @@ body: |
; CHECK-LABEL: name: eq
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
- ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY1]], 0, implicit $nzcv
- ; CHECK: $w0 = COPY [[CSELWr]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY1]], 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
@@ -48,13 +49,14 @@ body: |
; CHECK-LABEL: name: using_fcmp
; CHECK: liveins: $s0, $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
- ; CHECK: FCMPSri [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY]], 0, implicit $nzcv
- ; CHECK: $w0 = COPY [[CSELWr]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
+ ; CHECK-NEXT: FCMPSri [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY]], 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSELWr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(s32) = COPY $w1
%2:fpr(s32) = COPY $s0
%3:fpr(s32) = G_FCONSTANT float 0.000000e+00
@@ -78,11 +80,12 @@ body: |
; CHECK-LABEL: name: csinc
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY]], $wzr, 0, implicit $nzcv
- ; CHECK: $w0 = COPY [[CSINCWr]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY]], $wzr, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index 6f3df4551e56c..dbcdc52e4e727 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -6,13 +6,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_add_big
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -31,15 +31,15 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_add_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
- ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY [[UADDE]](s64)
- ; CHECK: $x2 = COPY [[UADDE2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: $x2 = COPY [[UADDE2]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -59,12 +59,12 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_add_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
- ; CHECK: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@@ -80,13 +80,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_add_narrowing
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -108,13 +108,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_add_narrowing_s65
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -136,13 +136,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_add
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
- ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
- ; CHECK: $q0 = COPY [[ADD]](<2 x s64>)
- ; CHECK: $q1 = COPY [[ADD1]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
+ ; CHECK-NEXT: $q0 = COPY [[ADD]](<2 x s64>)
+ ; CHECK-NEXT: $q1 = COPY [[ADD1]](<2 x s64>)
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
%2:_(<2 x s64>) = COPY $q2
@@ -161,15 +161,15 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_vector_add_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
- ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
- ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY2]]
- ; CHECK: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: $q0 = COPY [[ADD]](<2 x s64>)
- ; CHECK: $q1 = COPY [[ADD1]](<2 x s64>)
- ; CHECK: $q2 = COPY [[ADD2]](<2 x s64>)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $q0 = COPY [[ADD]](<2 x s64>)
+ ; CHECK-NEXT: $q1 = COPY [[ADD1]](<2 x s64>)
+ ; CHECK-NEXT: $q2 = COPY [[ADD2]](<2 x s64>)
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
%2:_(<2 x s64>) = COPY $q2
@@ -193,11 +193,12 @@ body: |
; CHECK-LABEL: name: add_v8i16
; CHECK: liveins: $q0, $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
- ; CHECK: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK: $q0 = COPY [[ADD]](<8 x s16>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[ADD]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = COPY $q1
%2:_(<8 x s16>) = G_ADD %0, %1
@@ -216,11 +217,12 @@ body: |
; CHECK-LABEL: name: add_v16i8
; CHECK: liveins: $q0, $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
- ; CHECK: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK: $q0 = COPY [[ADD]](<16 x s8>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $q0 = COPY [[ADD]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%2:_(<16 x s8>) = G_ADD %0, %1
@@ -239,11 +241,12 @@ body: |
; CHECK-LABEL: name: add_v4i16
; CHECK: liveins: $d0, $d1
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
- ; CHECK: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK: $d0 = COPY [[ADD]](<4 x s16>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[ADD]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
%2:_(<4 x s16>) = G_ADD %0, %1
@@ -259,11 +262,12 @@ body: |
; CHECK-LABEL: name: add_v8s8
; CHECK: liveins: $d0, $d1
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK: [[ADD:%[0-9]+]]:_(<8 x s8>) = G_ADD [[COPY]], [[COPY1]]
- ; CHECK: $d0 = COPY [[ADD]](<8 x s8>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s8>) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $d0 = COPY [[ADD]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
%2:_(<8 x s8>) = G_ADD %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
index afba01909be60..175f7158189ef 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
@@ -6,19 +6,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_icmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
- ; CHECK: $w0 = COPY [[ICMP]](s32)
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
- ; CHECK: $w0 = COPY [[ICMP1]](s32)
- ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
- ; CHECK: $w0 = COPY [[ICMP2]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[ICMP]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
+ ; CHECK-NEXT: $w0 = COPY [[ICMP1]](s32)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
+ ; CHECK-NEXT: $w0 = COPY [[ICMP2]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x0
%2:_(s8) = G_TRUNC %0(s64)
@@ -42,22 +42,24 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s128
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967296
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C1]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ICMP2]], [[ICMP]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[SELECT]](s32)
- ; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967296
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[SELECT]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC1]](s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%0:_(s128) = G_IMPLICIT_DEF
%1:_(s128) = G_CONSTANT i128 79228162514264337593543950336
@@ -80,20 +82,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s128_eq
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
- ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C]]
- ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND %cmp(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C]]
+ ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND %cmp(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%lhs:_(s128) = G_IMPLICIT_DEF
%rhs:_(s128) = G_IMPLICIT_DEF
@@ -112,26 +116,28 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s88_eq
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
- ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
- ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND %cmp(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
+ ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND %cmp(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%lhs:_(s88) = G_IMPLICIT_DEF
%rhs:_(s88) = G_IMPLICIT_DEF
@@ -150,26 +156,28 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s88_ne
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
- ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s64), [[C2]]
- ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND %cmp(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s64), [[C2]]
+ ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND %cmp(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%lhs:_(s88) = G_IMPLICIT_DEF
%rhs:_(s88) = G_IMPLICIT_DEF
@@ -188,27 +196,28 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s96_eq
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: {{ $}}
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
- ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
- ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND %cmp(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
+ ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND %cmp(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%lhs:_(s96) = G_IMPLICIT_DEF
%rhs:_(s96) = G_IMPLICIT_DEF
@@ -226,50 +235,52 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s318_eq
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[AND5:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[AND6:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[AND7:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[AND8:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND9:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND10:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND11:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND12:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[AND13:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[AND14:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[AND15:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND8]]
- ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND9]]
- ; CHECK: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[AND2]], [[AND10]]
- ; CHECK: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[AND3]], [[AND11]]
- ; CHECK: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[AND4]], [[AND12]]
- ; CHECK: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[AND5]], [[AND13]]
- ; CHECK: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[AND6]], [[AND14]]
- ; CHECK: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[AND7]], [[AND15]]
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
- ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
- ; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
- ; CHECK: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[XOR4]]
- ; CHECK: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[XOR5]]
- ; CHECK: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[XOR6]]
- ; CHECK: [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[XOR7]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR6]](s64), [[C2]]
- ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND %cmp(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND8]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND9]]
+ ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[AND2]], [[AND10]]
+ ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[AND3]], [[AND11]]
+ ; CHECK-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[AND4]], [[AND12]]
+ ; CHECK-NEXT: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[AND5]], [[AND13]]
+ ; CHECK-NEXT: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[AND6]], [[AND14]]
+ ; CHECK-NEXT: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[AND7]], [[AND15]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[XOR4]]
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[XOR5]]
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[XOR6]]
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[XOR7]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR6]](s64), [[C2]]
+ ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND %cmp(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%lhs:_(s318) = G_IMPLICIT_DEF
%rhs:_(s318) = G_IMPLICIT_DEF
@@ -287,34 +298,36 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_s158_eq
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1073741823
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND5:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
- ; CHECK: [[AND6:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
- ; CHECK: [[AND7:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND4]]
- ; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND5]]
- ; CHECK: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[AND2]], [[AND6]]
- ; CHECK: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[AND3]], [[AND7]]
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
- ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
- ; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR2]](s64), [[C2]]
- ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND %cmp(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1073741823
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND4]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND5]]
+ ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[AND2]], [[AND6]]
+ ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[AND3]], [[AND7]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR2]](s64), [[C2]]
+ ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND %cmp(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors:
; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%lhs:_(s158) = G_IMPLICIT_DEF
%rhs:_(s158) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
index 69715c2cef252..38b427124dd51 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
@@ -8,8 +8,8 @@ body: |
; CHECK-LABEL: name: test_freeze_s64
; CHECK: %x0:_(s64) = COPY $x0
- ; CHECK: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE %x0
- ; CHECK: $x0 = COPY [[FREEZE]](s64)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE %x0
+ ; CHECK-NEXT: $x0 = COPY [[FREEZE]](s64)
%x0:_(s64) = COPY $x0
%1:_(s64) = G_FREEZE %x0
$x0 = COPY %1(s64)
@@ -22,10 +22,10 @@ body: |
; CHECK-LABEL: name: test_freeze_v4s32
; CHECK: %q0:_(<4 x s32>) = COPY $q0
- ; CHECK: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE %q0
- ; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FREEZE]](<4 x s32>)
- ; CHECK: $x0 = COPY [[UV]](<2 x s32>)
- ; CHECK: $x1 = COPY [[UV1]](<2 x s32>)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE %q0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FREEZE]](<4 x s32>)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](<2 x s32>)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](<2 x s32>)
%q0:_(<4 x s32>) = COPY $q0
%0:_(<4 x s32>) = G_FREEZE %q0
%1:_(<2 x s32> ), %2:_(<2 x s32>) = G_UNMERGE_VALUES %0
@@ -39,10 +39,10 @@ body: |
; CHECK-LABEL: name: test_freeze_v4s64
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s64>) = G_FREEZE [[DEF]]
- ; CHECK: [[FREEZE1:%[0-9]+]]:_(<2 x s64>) = G_FREEZE [[DEF]]
- ; CHECK: $q0 = COPY [[FREEZE]](<2 x s64>)
- ; CHECK: $q1 = COPY [[FREEZE1]](<2 x s64>)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x s64>) = G_FREEZE [[DEF]]
+ ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(<2 x s64>) = G_FREEZE [[DEF]]
+ ; CHECK-NEXT: $q0 = COPY [[FREEZE]](<2 x s64>)
+ ; CHECK-NEXT: $q1 = COPY [[FREEZE1]](<2 x s64>)
%undef:_(<4 x s64>) = G_IMPLICIT_DEF
%0:_(<4 x s64>) = G_FREEZE %undef
%1:_(<2 x s64> ), %2:_(<2 x s64>) = G_UNMERGE_VALUES %0
@@ -57,10 +57,10 @@ body: |
; CHECK-LABEL: name: test_freeze_v2s32
; CHECK: %d0:_(<2 x s32>) = COPY $d0
- ; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE %d0
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FREEZE]](<2 x s32>)
- ; CHECK: $w0 = COPY [[UV]](s32)
- ; CHECK: $w1 = COPY [[UV1]](s32)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE %d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FREEZE]](<2 x s32>)
+ ; CHECK-NEXT: $w0 = COPY [[UV]](s32)
+ ; CHECK-NEXT: $w1 = COPY [[UV1]](s32)
%d0:_(<2 x s32>) = COPY $d0
%0:_(<2 x s32>) = G_FREEZE %d0
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0
@@ -75,10 +75,10 @@ body: |
; CHECK-LABEL: name: test_freeze_v8s8
; CHECK: %d0:_(<8 x s8>) = COPY $d0
- ; CHECK: [[FREEZE:%[0-9]+]]:_(<8 x s8>) = G_FREEZE %d0
- ; CHECK: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[FREEZE]](<8 x s8>)
- ; CHECK: $w0 = COPY [[UV]](<4 x s8>)
- ; CHECK: $w1 = COPY [[UV1]](<4 x s8>)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<8 x s8>) = G_FREEZE %d0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[FREEZE]](<8 x s8>)
+ ; CHECK-NEXT: $w0 = COPY [[UV]](<4 x s8>)
+ ; CHECK-NEXT: $w1 = COPY [[UV1]](<4 x s8>)
%d0:_(<8 x s8>) = COPY $d0
%0:_(<8 x s8>) = G_FREEZE %d0
%1:_(<4 x s8>), %2:_(<4 x s8>) = G_UNMERGE_VALUES %0
@@ -92,9 +92,9 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_freeze_s1
; CHECK: %x:_(s1) = G_IMPLICIT_DEF
- ; CHECK: %freeze:_(s1) = G_FREEZE %x
- ; CHECK: %ext:_(s64) = G_ZEXT %freeze(s1)
- ; CHECK: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: %freeze:_(s1) = G_FREEZE %x
+ ; CHECK-NEXT: %ext:_(s64) = G_ZEXT %freeze(s1)
+ ; CHECK-NEXT: $x0 = COPY %ext(s64)
%x:_(s1) = G_IMPLICIT_DEF
%freeze:_(s1) = G_FREEZE %x
%ext:_(s64) = G_ZEXT %freeze
@@ -107,11 +107,11 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_freeze_s2
; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
- ; CHECK: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
+ ; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: $x0 = COPY %ext(s64)
%x:_(s2) = G_IMPLICIT_DEF
%freeze:_(s2) = G_FREEZE %x
%ext:_(s64) = G_ZEXT %freeze
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index b7072ea85cf24..0666683608090 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -11,8 +11,8 @@ body: |
; CHECK-LABEL: name: test_inserts_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: $x0 = COPY [[COPY]](s64)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -31,14 +31,14 @@ body: |
; CHECK-LABEL: name: test_inserts_s96
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s32), [[DEF]](s32)
- ; CHECK: $x0 = COPY [[MV]](s64)
- ; CHECK: $x1 = COPY [[MV1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[MV]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[MV1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -59,509 +59,509 @@ body: |
; CHECK-LABEL: name: test_inserts_s65
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C]](s64)
- ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT1]], [[C1]](s64)
- ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT2]], [[C2]](s64)
- ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
- ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT3]], [[C3]](s64)
- ; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
- ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
- ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT4]], [[C4]](s64)
- ; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
- ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
- ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT5]], [[C5]](s64)
- ; CHECK: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
- ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
- ; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT6]], [[C6]](s64)
- ; CHECK: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
- ; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT7]], [[C]](s64)
- ; CHECK: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
- ; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT8]], [[C1]](s64)
- ; CHECK: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
- ; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT9]], [[C2]](s64)
- ; CHECK: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
- ; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT10]], [[C3]](s64)
- ; CHECK: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
- ; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT11]], [[C4]](s64)
- ; CHECK: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
- ; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT12]], [[C5]](s64)
- ; CHECK: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
- ; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT13]], [[C6]](s64)
- ; CHECK: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
- ; CHECK: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT14]], [[C]](s64)
- ; CHECK: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
- ; CHECK: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT15]], [[C1]](s64)
- ; CHECK: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
- ; CHECK: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT16]], [[C2]](s64)
- ; CHECK: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
- ; CHECK: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT17]], [[C3]](s64)
- ; CHECK: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
- ; CHECK: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT18]], [[C4]](s64)
- ; CHECK: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
- ; CHECK: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT19]], [[C5]](s64)
- ; CHECK: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
- ; CHECK: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT20]], [[C6]](s64)
- ; CHECK: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
- ; CHECK: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT21]], [[C]](s64)
- ; CHECK: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
- ; CHECK: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT22]], [[C1]](s64)
- ; CHECK: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
- ; CHECK: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT23]], [[C2]](s64)
- ; CHECK: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
- ; CHECK: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT24]], [[C3]](s64)
- ; CHECK: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
- ; CHECK: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT25]], [[C4]](s64)
- ; CHECK: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
- ; CHECK: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT26]], [[C5]](s64)
- ; CHECK: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
- ; CHECK: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT27]], [[C6]](s64)
- ; CHECK: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
- ; CHECK: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT28]], [[C]](s64)
- ; CHECK: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
- ; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT29]], [[C1]](s64)
- ; CHECK: [[ZEXT30:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
- ; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT30]], [[C2]](s64)
- ; CHECK: [[ZEXT31:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
- ; CHECK: [[LSHR31:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT31]], [[C3]](s64)
- ; CHECK: [[ZEXT32:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
- ; CHECK: [[LSHR32:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT32]], [[C4]](s64)
- ; CHECK: [[ZEXT33:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
- ; CHECK: [[LSHR33:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT33]], [[C5]](s64)
- ; CHECK: [[ZEXT34:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
- ; CHECK: [[LSHR34:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT34]], [[C6]](s64)
- ; CHECK: [[ZEXT35:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
- ; CHECK: [[LSHR35:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT35]], [[C]](s64)
- ; CHECK: [[ZEXT36:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
- ; CHECK: [[LSHR36:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT36]], [[C1]](s64)
- ; CHECK: [[ZEXT37:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
- ; CHECK: [[LSHR37:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT37]], [[C2]](s64)
- ; CHECK: [[ZEXT38:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
- ; CHECK: [[LSHR38:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT38]], [[C3]](s64)
- ; CHECK: [[ZEXT39:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
- ; CHECK: [[LSHR39:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT39]], [[C4]](s64)
- ; CHECK: [[ZEXT40:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
- ; CHECK: [[LSHR40:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT40]], [[C5]](s64)
- ; CHECK: [[ZEXT41:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
- ; CHECK: [[LSHR41:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT41]], [[C6]](s64)
- ; CHECK: [[ZEXT42:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
- ; CHECK: [[LSHR42:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT42]], [[C]](s64)
- ; CHECK: [[ZEXT43:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
- ; CHECK: [[LSHR43:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT43]], [[C1]](s64)
- ; CHECK: [[ZEXT44:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
- ; CHECK: [[LSHR44:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT44]], [[C2]](s64)
- ; CHECK: [[ZEXT45:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
- ; CHECK: [[LSHR45:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT45]], [[C3]](s64)
- ; CHECK: [[ZEXT46:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
- ; CHECK: [[LSHR46:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT46]], [[C4]](s64)
- ; CHECK: [[ZEXT47:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
- ; CHECK: [[LSHR47:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT47]], [[C5]](s64)
- ; CHECK: [[ZEXT48:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
- ; CHECK: [[LSHR48:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT48]], [[C6]](s64)
- ; CHECK: [[ZEXT49:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
- ; CHECK: [[LSHR49:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT49]], [[C]](s64)
- ; CHECK: [[ZEXT50:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
- ; CHECK: [[LSHR50:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT50]], [[C1]](s64)
- ; CHECK: [[ZEXT51:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
- ; CHECK: [[LSHR51:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT51]], [[C2]](s64)
- ; CHECK: [[ZEXT52:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
- ; CHECK: [[LSHR52:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT52]], [[C3]](s64)
- ; CHECK: [[ZEXT53:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
- ; CHECK: [[LSHR53:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT53]], [[C4]](s64)
- ; CHECK: [[ZEXT54:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
- ; CHECK: [[LSHR54:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT54]], [[C5]](s64)
- ; CHECK: [[ZEXT55:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
- ; CHECK: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT55]], [[C6]](s64)
- ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s64)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C7]]
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C7]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s64)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C7]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s64)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C7]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C3]](s64)
- ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C7]]
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s64)
- ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C7]]
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s64)
- ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C7]]
- ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s64)
- ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C7]]
- ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s64)
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C7]]
- ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL7]]
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C7]]
- ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s64)
- ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C7]]
- ; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s64)
- ; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C7]]
- ; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C3]](s64)
- ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C7]]
- ; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s64)
- ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C7]]
- ; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s64)
- ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C7]]
- ; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s64)
- ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
- ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C7]]
- ; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C]](s64)
- ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
- ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C7]]
- ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL14]]
- ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C7]]
- ; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s64)
- ; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
- ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C7]]
- ; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s64)
- ; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C7]]
- ; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C3]](s64)
- ; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C7]]
- ; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s64)
- ; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
- ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C7]]
- ; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s64)
- ; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C7]]
- ; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s64)
- ; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
- ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C7]]
- ; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C]](s64)
- ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
- ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C7]]
- ; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL21]]
- ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C7]]
- ; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s64)
- ; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C7]]
- ; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s64)
- ; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
- ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C7]]
- ; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C3]](s64)
- ; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
- ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C7]]
- ; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C4]](s64)
- ; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
- ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C7]]
- ; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C5]](s64)
- ; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
- ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C7]]
- ; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C6]](s64)
- ; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
- ; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C7]]
- ; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C]](s64)
- ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
- ; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C7]]
- ; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[SHL28]]
- ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C7]]
- ; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C1]](s64)
- ; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
- ; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C7]]
- ; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C2]](s64)
- ; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
- ; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[LSHR31]], [[C7]]
- ; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C3]](s64)
- ; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]]
- ; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[LSHR32]], [[C7]]
- ; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C4]](s64)
- ; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
- ; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[LSHR33]], [[C7]]
- ; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C5]](s64)
- ; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
- ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[LSHR34]], [[C7]]
- ; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C6]](s64)
- ; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
- ; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
- ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[LSHR35]], [[C7]]
- ; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C]](s64)
- ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
- ; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C7]]
- ; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[SHL35]]
- ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[LSHR36]], [[C7]]
- ; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C1]](s64)
- ; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
- ; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[LSHR37]], [[C7]]
- ; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C2]](s64)
- ; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
- ; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[LSHR38]], [[C7]]
- ; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C3]](s64)
- ; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
- ; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[LSHR39]], [[C7]]
- ; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C4]](s64)
- ; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
- ; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[LSHR40]], [[C7]]
- ; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C5]](s64)
- ; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
- ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[LSHR41]], [[C7]]
- ; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C6]](s64)
- ; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
- ; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR41]](s32)
- ; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[LSHR42]], [[C7]]
- ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C]](s64)
- ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
- ; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C7]]
- ; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[SHL42]]
- ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[LSHR43]], [[C7]]
- ; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C1]](s64)
- ; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
- ; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[LSHR44]], [[C7]]
- ; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C2]](s64)
- ; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
- ; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[LSHR45]], [[C7]]
- ; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C3]](s64)
- ; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
- ; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[LSHR46]], [[C7]]
- ; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C4]](s64)
- ; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
- ; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[LSHR47]], [[C7]]
- ; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C5]](s64)
- ; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
- ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[LSHR48]], [[C7]]
- ; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C6]](s64)
- ; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
- ; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[OR48]](s32)
- ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[LSHR49]], [[C7]]
- ; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C]](s64)
- ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
- ; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C7]]
- ; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[SHL49]]
- ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[LSHR50]], [[C7]]
- ; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C1]](s64)
- ; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
- ; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[LSHR51]], [[C7]]
- ; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C2]](s64)
- ; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
- ; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[LSHR52]], [[C7]]
- ; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C3]](s64)
- ; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
- ; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[LSHR53]], [[C7]]
- ; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C4]](s64)
- ; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
- ; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[LSHR54]], [[C7]]
- ; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C5]](s64)
- ; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
- ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[LSHR55]], [[C7]]
- ; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C6]](s64)
- ; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
- ; CHECK: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
- ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8)
- ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s64)
- ; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[TRUNC8]], [[C7]]
- ; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[SHL56]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s64)
- ; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s64)
- ; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C3]](s64)
- ; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C4]](s64)
- ; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C5]](s64)
- ; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C6]](s64)
- ; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[OR61]], [[SHL62]]
- ; CHECK: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[OR62]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s64)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[COPY10]], [[SHL63]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C1]](s64)
- ; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C2]](s64)
- ; CHECK: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C3]](s64)
- ; CHECK: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C4]](s64)
- ; CHECK: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C5]](s64)
- ; CHECK: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C6]](s64)
- ; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]]
- ; CHECK: [[TRUNC10:%[0-9]+]]:_(s8) = G_TRUNC [[OR69]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C]](s64)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[OR70:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL70]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s64)
- ; CHECK: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s64)
- ; CHECK: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C3]](s64)
- ; CHECK: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C4]](s64)
- ; CHECK: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C5]](s64)
- ; CHECK: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C6]](s64)
- ; CHECK: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]]
- ; CHECK: [[TRUNC11:%[0-9]+]]:_(s8) = G_TRUNC [[OR76]](s32)
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C]](s64)
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[OR77:%[0-9]+]]:_(s32) = G_OR [[COPY26]], [[SHL77]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY27]], [[C1]](s64)
- ; CHECK: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C2]](s64)
- ; CHECK: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]]
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C3]](s64)
- ; CHECK: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY30]], [[C4]](s64)
- ; CHECK: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[C5]](s64)
- ; CHECK: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]]
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY32]], [[C6]](s64)
- ; CHECK: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]]
- ; CHECK: [[TRUNC12:%[0-9]+]]:_(s8) = G_TRUNC [[OR83]](s32)
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[C]](s64)
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[OR84:%[0-9]+]]:_(s32) = G_OR [[COPY34]], [[SHL84]]
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY35]], [[C1]](s64)
- ; CHECK: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]]
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[C2]](s64)
- ; CHECK: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]]
- ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY37]], [[C3]](s64)
- ; CHECK: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]]
- ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[C4]](s64)
- ; CHECK: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]]
- ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY39]], [[C5]](s64)
- ; CHECK: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]]
- ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C6]](s64)
- ; CHECK: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]]
- ; CHECK: [[TRUNC13:%[0-9]+]]:_(s8) = G_TRUNC [[OR90]](s32)
- ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY41]], [[C]](s64)
- ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[OR91:%[0-9]+]]:_(s32) = G_OR [[COPY42]], [[SHL91]]
- ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY43]], [[C1]](s64)
- ; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]]
- ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C2]](s64)
- ; CHECK: [[OR93:%[0-9]+]]:_(s32) = G_OR [[OR92]], [[SHL93]]
- ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY45]], [[C3]](s64)
- ; CHECK: [[OR94:%[0-9]+]]:_(s32) = G_OR [[OR93]], [[SHL94]]
- ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY46]], [[C4]](s64)
- ; CHECK: [[OR95:%[0-9]+]]:_(s32) = G_OR [[OR94]], [[SHL95]]
- ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY47]], [[C5]](s64)
- ; CHECK: [[OR96:%[0-9]+]]:_(s32) = G_OR [[OR95]], [[SHL96]]
- ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY48]], [[C6]](s64)
- ; CHECK: [[OR97:%[0-9]+]]:_(s32) = G_OR [[OR96]], [[SHL97]]
- ; CHECK: [[TRUNC14:%[0-9]+]]:_(s8) = G_TRUNC [[OR97]](s32)
- ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY49]], [[C]](s64)
- ; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[OR98:%[0-9]+]]:_(s32) = G_OR [[COPY50]], [[SHL98]]
- ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY51]], [[C1]](s64)
- ; CHECK: [[OR99:%[0-9]+]]:_(s32) = G_OR [[OR98]], [[SHL99]]
- ; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY52]], [[C2]](s64)
- ; CHECK: [[OR100:%[0-9]+]]:_(s32) = G_OR [[OR99]], [[SHL100]]
- ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[COPY53]], [[C3]](s64)
- ; CHECK: [[OR101:%[0-9]+]]:_(s32) = G_OR [[OR100]], [[SHL101]]
- ; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[COPY54]], [[C4]](s64)
- ; CHECK: [[OR102:%[0-9]+]]:_(s32) = G_OR [[OR101]], [[SHL102]]
- ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C5]](s64)
- ; CHECK: [[OR103:%[0-9]+]]:_(s32) = G_OR [[OR102]], [[SHL103]]
- ; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[COPY56]], [[C6]](s64)
- ; CHECK: [[OR104:%[0-9]+]]:_(s32) = G_OR [[OR103]], [[SHL104]]
- ; CHECK: [[TRUNC15:%[0-9]+]]:_(s8) = G_TRUNC [[OR104]](s32)
- ; CHECK: [[SHL105:%[0-9]+]]:_(s32) = G_SHL [[C8]], [[C]](s64)
- ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[OR105:%[0-9]+]]:_(s32) = G_OR [[COPY57]], [[SHL105]]
- ; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[COPY58]], [[C1]](s64)
- ; CHECK: [[OR106:%[0-9]+]]:_(s32) = G_OR [[OR105]], [[SHL106]]
- ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[COPY59]], [[C2]](s64)
- ; CHECK: [[OR107:%[0-9]+]]:_(s32) = G_OR [[OR106]], [[SHL107]]
- ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[COPY60]], [[C3]](s64)
- ; CHECK: [[OR108:%[0-9]+]]:_(s32) = G_OR [[OR107]], [[SHL108]]
- ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[COPY61]], [[C4]](s64)
- ; CHECK: [[OR109:%[0-9]+]]:_(s32) = G_OR [[OR108]], [[SHL109]]
- ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[COPY62]], [[C5]](s64)
- ; CHECK: [[OR110:%[0-9]+]]:_(s32) = G_OR [[OR109]], [[SHL110]]
- ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[COPY63]], [[C6]](s64)
- ; CHECK: [[OR111:%[0-9]+]]:_(s32) = G_OR [[OR110]], [[SHL111]]
- ; CHECK: [[TRUNC16:%[0-9]+]]:_(s8) = G_TRUNC [[OR111]](s32)
- ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC9]](s8), [[TRUNC10]](s8), [[TRUNC11]](s8), [[TRUNC12]](s8), [[TRUNC13]](s8), [[TRUNC14]](s8), [[TRUNC15]](s8), [[TRUNC16]](s8)
- ; CHECK: $x0 = COPY [[MV]](s64)
- ; CHECK: $x1 = COPY [[MV1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT1]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT2]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT3]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT4]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT5]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT6]], [[C6]](s64)
+ ; CHECK-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT7]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT8]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT9]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT10]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT11]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT12]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT13]], [[C6]](s64)
+ ; CHECK-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT14]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT15]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT16]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT17]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT18]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT19]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT20]], [[C6]](s64)
+ ; CHECK-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT21]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT22]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT23]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT24]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT25]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT26]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT27]], [[C6]](s64)
+ ; CHECK-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT28]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT29]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT30:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT30]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT31:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[LSHR31:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT31]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT32:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[LSHR32:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT32]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT33:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[LSHR33:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT33]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT34:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[LSHR34:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT34]], [[C6]](s64)
+ ; CHECK-NEXT: [[ZEXT35:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[LSHR35:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT35]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT36:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[LSHR36:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT36]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT37:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[LSHR37:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT37]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT38:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[LSHR38:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT38]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT39:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[LSHR39:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT39]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT40:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[LSHR40:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT40]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT41:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[LSHR41:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT41]], [[C6]](s64)
+ ; CHECK-NEXT: [[ZEXT42:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[LSHR42:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT42]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT43:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[LSHR43:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT43]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT44:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[LSHR44:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT44]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT45:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[LSHR45:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT45]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT46:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[LSHR46:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT46]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT47:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[LSHR47:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT47]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT48:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[LSHR48:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT48]], [[C6]](s64)
+ ; CHECK-NEXT: [[ZEXT49:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[LSHR49:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT49]], [[C]](s64)
+ ; CHECK-NEXT: [[ZEXT50:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[LSHR50:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT50]], [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXT51:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[LSHR51:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT51]], [[C2]](s64)
+ ; CHECK-NEXT: [[ZEXT52:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[LSHR52:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT52]], [[C3]](s64)
+ ; CHECK-NEXT: [[ZEXT53:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[LSHR53:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT53]], [[C4]](s64)
+ ; CHECK-NEXT: [[ZEXT54:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[LSHR54:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT54]], [[C5]](s64)
+ ; CHECK-NEXT: [[ZEXT55:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT55]], [[C6]](s64)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C7]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C7]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C7]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C7]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C7]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C7]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C7]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C7]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C7]]
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL7]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C7]]
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C7]]
+ ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C7]]
+ ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C7]]
+ ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C7]]
+ ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C7]]
+ ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
+ ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C7]]
+ ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
+ ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C7]]
+ ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL14]]
+ ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C7]]
+ ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
+ ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C7]]
+ ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
+ ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C7]]
+ ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
+ ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C7]]
+ ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
+ ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C7]]
+ ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
+ ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C7]]
+ ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
+ ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C7]]
+ ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
+ ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C7]]
+ ; CHECK-NEXT: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL21]]
+ ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C7]]
+ ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
+ ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C7]]
+ ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
+ ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C7]]
+ ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
+ ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C7]]
+ ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
+ ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C7]]
+ ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
+ ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C7]]
+ ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
+ ; CHECK-NEXT: [[AND32:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C7]]
+ ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
+ ; CHECK-NEXT: [[AND33:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C7]]
+ ; CHECK-NEXT: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[SHL28]]
+ ; CHECK-NEXT: [[AND34:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C7]]
+ ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
+ ; CHECK-NEXT: [[AND35:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C7]]
+ ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
+ ; CHECK-NEXT: [[AND36:%[0-9]+]]:_(s32) = G_AND [[LSHR31]], [[C7]]
+ ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]]
+ ; CHECK-NEXT: [[AND37:%[0-9]+]]:_(s32) = G_AND [[LSHR32]], [[C7]]
+ ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
+ ; CHECK-NEXT: [[AND38:%[0-9]+]]:_(s32) = G_AND [[LSHR33]], [[C7]]
+ ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
+ ; CHECK-NEXT: [[AND39:%[0-9]+]]:_(s32) = G_AND [[LSHR34]], [[C7]]
+ ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
+ ; CHECK-NEXT: [[AND40:%[0-9]+]]:_(s32) = G_AND [[LSHR35]], [[C7]]
+ ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
+ ; CHECK-NEXT: [[AND41:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C7]]
+ ; CHECK-NEXT: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[SHL35]]
+ ; CHECK-NEXT: [[AND42:%[0-9]+]]:_(s32) = G_AND [[LSHR36]], [[C7]]
+ ; CHECK-NEXT: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
+ ; CHECK-NEXT: [[AND43:%[0-9]+]]:_(s32) = G_AND [[LSHR37]], [[C7]]
+ ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
+ ; CHECK-NEXT: [[AND44:%[0-9]+]]:_(s32) = G_AND [[LSHR38]], [[C7]]
+ ; CHECK-NEXT: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
+ ; CHECK-NEXT: [[AND45:%[0-9]+]]:_(s32) = G_AND [[LSHR39]], [[C7]]
+ ; CHECK-NEXT: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
+ ; CHECK-NEXT: [[AND46:%[0-9]+]]:_(s32) = G_AND [[LSHR40]], [[C7]]
+ ; CHECK-NEXT: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
+ ; CHECK-NEXT: [[AND47:%[0-9]+]]:_(s32) = G_AND [[LSHR41]], [[C7]]
+ ; CHECK-NEXT: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR41]](s32)
+ ; CHECK-NEXT: [[AND48:%[0-9]+]]:_(s32) = G_AND [[LSHR42]], [[C7]]
+ ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
+ ; CHECK-NEXT: [[AND49:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C7]]
+ ; CHECK-NEXT: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[SHL42]]
+ ; CHECK-NEXT: [[AND50:%[0-9]+]]:_(s32) = G_AND [[LSHR43]], [[C7]]
+ ; CHECK-NEXT: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
+ ; CHECK-NEXT: [[AND51:%[0-9]+]]:_(s32) = G_AND [[LSHR44]], [[C7]]
+ ; CHECK-NEXT: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
+ ; CHECK-NEXT: [[AND52:%[0-9]+]]:_(s32) = G_AND [[LSHR45]], [[C7]]
+ ; CHECK-NEXT: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
+ ; CHECK-NEXT: [[AND53:%[0-9]+]]:_(s32) = G_AND [[LSHR46]], [[C7]]
+ ; CHECK-NEXT: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
+ ; CHECK-NEXT: [[AND54:%[0-9]+]]:_(s32) = G_AND [[LSHR47]], [[C7]]
+ ; CHECK-NEXT: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
+ ; CHECK-NEXT: [[AND55:%[0-9]+]]:_(s32) = G_AND [[LSHR48]], [[C7]]
+ ; CHECK-NEXT: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[OR48]](s32)
+ ; CHECK-NEXT: [[AND56:%[0-9]+]]:_(s32) = G_AND [[LSHR49]], [[C7]]
+ ; CHECK-NEXT: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C]](s64)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
+ ; CHECK-NEXT: [[AND57:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C7]]
+ ; CHECK-NEXT: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[SHL49]]
+ ; CHECK-NEXT: [[AND58:%[0-9]+]]:_(s32) = G_AND [[LSHR50]], [[C7]]
+ ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
+ ; CHECK-NEXT: [[AND59:%[0-9]+]]:_(s32) = G_AND [[LSHR51]], [[C7]]
+ ; CHECK-NEXT: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
+ ; CHECK-NEXT: [[AND60:%[0-9]+]]:_(s32) = G_AND [[LSHR52]], [[C7]]
+ ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
+ ; CHECK-NEXT: [[AND61:%[0-9]+]]:_(s32) = G_AND [[LSHR53]], [[C7]]
+ ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
+ ; CHECK-NEXT: [[AND62:%[0-9]+]]:_(s32) = G_AND [[LSHR54]], [[C7]]
+ ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
+ ; CHECK-NEXT: [[AND63:%[0-9]+]]:_(s32) = G_AND [[LSHR55]], [[C7]]
+ ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s64)
+ ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[AND64:%[0-9]+]]:_(s32) = G_AND [[TRUNC8]], [[C7]]
+ ; CHECK-NEXT: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[SHL56]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR62:%[0-9]+]]:_(s32) = G_OR [[OR61]], [[SHL62]]
+ ; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[OR62]](s32)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[OR63:%[0-9]+]]:_(s32) = G_OR [[COPY10]], [[SHL63]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]]
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]]
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]]
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]]
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]]
+ ; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(s8) = G_TRUNC [[OR69]](s32)
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[OR70:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL70]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]]
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]]
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]]
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]]
+ ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]]
+ ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]]
+ ; CHECK-NEXT: [[TRUNC11:%[0-9]+]]:_(s8) = G_TRUNC [[OR76]](s32)
+ ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[OR77:%[0-9]+]]:_(s32) = G_OR [[COPY26]], [[SHL77]]
+ ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY27]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]]
+ ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]]
+ ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]]
+ ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY30]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]]
+ ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]]
+ ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY32]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]]
+ ; CHECK-NEXT: [[TRUNC12:%[0-9]+]]:_(s8) = G_TRUNC [[OR83]](s32)
+ ; CHECK-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[OR84:%[0-9]+]]:_(s32) = G_OR [[COPY34]], [[SHL84]]
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY35]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]]
+ ; CHECK-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]]
+ ; CHECK-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY37]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]]
+ ; CHECK-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]]
+ ; CHECK-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY39]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]]
+ ; CHECK-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]]
+ ; CHECK-NEXT: [[TRUNC13:%[0-9]+]]:_(s8) = G_TRUNC [[OR90]](s32)
+ ; CHECK-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY41]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[OR91:%[0-9]+]]:_(s32) = G_OR [[COPY42]], [[SHL91]]
+ ; CHECK-NEXT: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY43]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]]
+ ; CHECK-NEXT: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR93:%[0-9]+]]:_(s32) = G_OR [[OR92]], [[SHL93]]
+ ; CHECK-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY45]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR94:%[0-9]+]]:_(s32) = G_OR [[OR93]], [[SHL94]]
+ ; CHECK-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY46]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR95:%[0-9]+]]:_(s32) = G_OR [[OR94]], [[SHL95]]
+ ; CHECK-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY47]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR96:%[0-9]+]]:_(s32) = G_OR [[OR95]], [[SHL96]]
+ ; CHECK-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY48]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR97:%[0-9]+]]:_(s32) = G_OR [[OR96]], [[SHL97]]
+ ; CHECK-NEXT: [[TRUNC14:%[0-9]+]]:_(s8) = G_TRUNC [[OR97]](s32)
+ ; CHECK-NEXT: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY49]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[OR98:%[0-9]+]]:_(s32) = G_OR [[COPY50]], [[SHL98]]
+ ; CHECK-NEXT: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY51]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR99:%[0-9]+]]:_(s32) = G_OR [[OR98]], [[SHL99]]
+ ; CHECK-NEXT: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY52]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR100:%[0-9]+]]:_(s32) = G_OR [[OR99]], [[SHL100]]
+ ; CHECK-NEXT: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[COPY53]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR101:%[0-9]+]]:_(s32) = G_OR [[OR100]], [[SHL101]]
+ ; CHECK-NEXT: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[COPY54]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR102:%[0-9]+]]:_(s32) = G_OR [[OR101]], [[SHL102]]
+ ; CHECK-NEXT: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR103:%[0-9]+]]:_(s32) = G_OR [[OR102]], [[SHL103]]
+ ; CHECK-NEXT: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[COPY56]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR104:%[0-9]+]]:_(s32) = G_OR [[OR103]], [[SHL104]]
+ ; CHECK-NEXT: [[TRUNC15:%[0-9]+]]:_(s8) = G_TRUNC [[OR104]](s32)
+ ; CHECK-NEXT: [[SHL105:%[0-9]+]]:_(s32) = G_SHL [[C8]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[OR105:%[0-9]+]]:_(s32) = G_OR [[COPY57]], [[SHL105]]
+ ; CHECK-NEXT: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[COPY58]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR106:%[0-9]+]]:_(s32) = G_OR [[OR105]], [[SHL106]]
+ ; CHECK-NEXT: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[COPY59]], [[C2]](s64)
+ ; CHECK-NEXT: [[OR107:%[0-9]+]]:_(s32) = G_OR [[OR106]], [[SHL107]]
+ ; CHECK-NEXT: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[COPY60]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR108:%[0-9]+]]:_(s32) = G_OR [[OR107]], [[SHL108]]
+ ; CHECK-NEXT: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[COPY61]], [[C4]](s64)
+ ; CHECK-NEXT: [[OR109:%[0-9]+]]:_(s32) = G_OR [[OR108]], [[SHL109]]
+ ; CHECK-NEXT: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[COPY62]], [[C5]](s64)
+ ; CHECK-NEXT: [[OR110:%[0-9]+]]:_(s32) = G_OR [[OR109]], [[SHL110]]
+ ; CHECK-NEXT: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK-NEXT: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[COPY63]], [[C6]](s64)
+ ; CHECK-NEXT: [[OR111:%[0-9]+]]:_(s32) = G_OR [[OR110]], [[SHL111]]
+ ; CHECK-NEXT: [[TRUNC16:%[0-9]+]]:_(s8) = G_TRUNC [[OR111]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC9]](s8), [[TRUNC10]](s8), [[TRUNC11]](s8), [[TRUNC12]](s8), [[TRUNC13]](s8), [[TRUNC14]](s8), [[TRUNC15]](s8), [[TRUNC16]](s8)
+ ; CHECK-NEXT: $x0 = COPY [[MV]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[MV1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -581,11 +581,11 @@ body: |
liveins: $w0, $w1
; CHECK-LABEL: name: s1_s32_legal
; CHECK: %val1:_(s32) = COPY $w0
- ; CHECK: %val2:_(s32) = COPY $w1
- ; CHECK: %op:_(s1) = G_TRUNC %val2(s32)
- ; CHECK: %ins:_(s32) = G_INSERT %val1, %op(s1), 0
- ; CHECK: $w0 = COPY %ins(s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: %val2:_(s32) = COPY $w1
+ ; CHECK-NEXT: %op:_(s1) = G_TRUNC %val2(s32)
+ ; CHECK-NEXT: %ins:_(s32) = G_INSERT %val1, %op(s1), 0
+ ; CHECK-NEXT: $w0 = COPY %ins(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val1:_(s32) = COPY $w0
%val2:_(s32) = COPY $w1
%op:_(s1) = G_TRUNC %val2
@@ -600,10 +600,10 @@ body: |
liveins: $w0, $b0
; CHECK-LABEL: name: s8_s32_legal
; CHECK: %val:_(s32) = COPY $w0
- ; CHECK: %op:_(s8) = COPY $b0
- ; CHECK: %ins:_(s32) = G_INSERT %val, %op(s8), 0
- ; CHECK: $w0 = COPY %ins(s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: %op:_(s8) = COPY $b0
+ ; CHECK-NEXT: %ins:_(s32) = G_INSERT %val, %op(s8), 0
+ ; CHECK-NEXT: $w0 = COPY %ins(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
%op:_(s8) = COPY $b0
%ins:_(s32) = G_INSERT %val, %op(s8), 0
@@ -617,10 +617,10 @@ body: |
liveins: $w0, $h0
; CHECK-LABEL: name: s16_s32_legal
; CHECK: %val:_(s32) = COPY $w0
- ; CHECK: %op:_(s16) = COPY $h0
- ; CHECK: %ins:_(s32) = G_INSERT %val, %op(s16), 0
- ; CHECK: $w0 = COPY %ins(s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: %op:_(s16) = COPY $h0
+ ; CHECK-NEXT: %ins:_(s32) = G_INSERT %val, %op(s16), 0
+ ; CHECK-NEXT: $w0 = COPY %ins(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
%op:_(s16) = COPY $h0
%ins:_(s32) = G_INSERT %val, %op(s16), 0
@@ -634,10 +634,10 @@ body: |
liveins: $x0, $w0
; CHECK-LABEL: name: s32_s64_legal
; CHECK: %val:_(s64) = COPY $x0
- ; CHECK: %op:_(s32) = COPY $w0
- ; CHECK: %ins:_(s64) = G_INSERT %val, %op(s32), 0
- ; CHECK: $x0 = COPY %ins(s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: %op:_(s32) = COPY $w0
+ ; CHECK-NEXT: %ins:_(s64) = G_INSERT %val, %op(s32), 0
+ ; CHECK-NEXT: $x0 = COPY %ins(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%val:_(s64) = COPY $x0
%op:_(s32) = COPY $w0
%ins:_(s64) = G_INSERT %val, %op(s32), 0
@@ -651,10 +651,10 @@ body: |
liveins: $x0, $w0
; CHECK-LABEL: name: s32_p0_legal
; CHECK: %val:_(p0) = COPY $x0
- ; CHECK: %op:_(s32) = COPY $w0
- ; CHECK: %ins:_(p0) = G_INSERT %val, %op(s32), 0
- ; CHECK: $x0 = COPY %ins(p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: %op:_(s32) = COPY $w0
+ ; CHECK-NEXT: %ins:_(p0) = G_INSERT %val, %op(s32), 0
+ ; CHECK-NEXT: $x0 = COPY %ins(p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%val:_(p0) = COPY $x0
%op:_(s32) = COPY $w0
%ins:_(p0) = G_INSERT %val, %op(s32), 0
@@ -668,12 +668,12 @@ body: |
liveins: $q0, $w0
; CHECK-LABEL: name: s32_s128
; CHECK: %val:_(s128) = COPY $q0
- ; CHECK: %op:_(s32) = COPY $w0
- ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %val(s128)
- ; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[UV]], %op(s32), 0
- ; CHECK: %ins:_(s128) = G_MERGE_VALUES [[INSERT]](s64), [[UV1]](s64)
- ; CHECK: $q0 = COPY %ins(s128)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: %op:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %val(s128)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[UV]], %op(s32), 0
+ ; CHECK-NEXT: %ins:_(s128) = G_MERGE_VALUES [[INSERT]](s64), [[UV1]](s64)
+ ; CHECK-NEXT: $q0 = COPY %ins(s128)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%val:_(s128) = COPY $q0
%op:_(s32) = COPY $w0
%ins:_(s128) = G_INSERT %val, %op(s32), 0
@@ -687,13 +687,13 @@ body: |
liveins: $q0, $w0
; CHECK-LABEL: name: s1_s128
; CHECK: %val1:_(s128) = COPY $q0
- ; CHECK: %val2:_(s32) = COPY $w1
- ; CHECK: %op:_(s1) = G_TRUNC %val2(s32)
- ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %val1(s128)
- ; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[UV]], %op(s1), 0
- ; CHECK: %ins:_(s128) = G_MERGE_VALUES [[INSERT]](s64), [[UV1]](s64)
- ; CHECK: $q0 = COPY %ins(s128)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: %val2:_(s32) = COPY $w1
+ ; CHECK-NEXT: %op:_(s1) = G_TRUNC %val2(s32)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %val1(s128)
+ ; CHECK-NEXT: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[UV]], %op(s1), 0
+ ; CHECK-NEXT: %ins:_(s128) = G_MERGE_VALUES [[INSERT]](s64), [[UV1]](s64)
+ ; CHECK-NEXT: $q0 = COPY %ins(s128)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%val1:_(s128) = COPY $q0
%val2:_(s32) = COPY $w1
%op:_(s1) = G_TRUNC %val2
@@ -710,11 +710,11 @@ body: |
; CHECK-LABEL: name: s4_s32
; CHECK: %val1:_(s32) = COPY $w0
- ; CHECK: %val2:_(s32) = COPY $w1
- ; CHECK: %op:_(s4) = G_TRUNC %val2(s32)
- ; CHECK: %ins:_(s32) = G_INSERT %val1, %op(s4), 0
- ; CHECK: $w0 = COPY %ins(s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: %val2:_(s32) = COPY $w1
+ ; CHECK-NEXT: %op:_(s4) = G_TRUNC %val2(s32)
+ ; CHECK-NEXT: %ins:_(s32) = G_INSERT %val1, %op(s4), 0
+ ; CHECK-NEXT: $w0 = COPY %ins(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%val1:_(s32) = COPY $w0
%val2:_(s32) = COPY $w1
%op:_(s4) = G_TRUNC %val2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
index a9968b6e8bea0..505a5a61be979 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
@@ -14,13 +14,14 @@ body: |
; CHECK-LABEL: name: smin_s32
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_SMIN %0, %1
@@ -41,13 +42,14 @@ body: |
; CHECK-LABEL: name: smin_s64
; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_SMIN %0, %1
@@ -68,13 +70,14 @@ body: |
; CHECK-LABEL: name: smax_s32
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_SMAX %0, %1
@@ -95,13 +98,14 @@ body: |
; CHECK-LABEL: name: smax_s64
; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_SMAX %0, %1
@@ -124,13 +128,14 @@ body: |
; CHECK-LABEL: name: umin_s32
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_UMIN %0, %1
@@ -151,13 +156,14 @@ body: |
; CHECK-LABEL: name: umin_s64
; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_UMIN %0, %1
@@ -178,13 +184,14 @@ body: |
; CHECK-LABEL: name: umax_s32
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_UMAX %0, %1
@@ -205,13 +212,14 @@ body: |
; CHECK-LABEL: name: umax_s64
; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_UMAX %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index 2112497fa607c..fa3339d869ed1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -8,28 +8,28 @@ body: |
; CHECK-LABEL: name: test_load
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASSERT_ZEXT]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT1]](s32)
- ; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD2]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT2]](s32)
- ; CHECK: $w0 = COPY [[ANYEXT1]](s32)
- ; CHECK: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
- ; CHECK: $x0 = COPY [[LOAD3]](s64)
- ; CHECK: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0))
- ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD4]](p0)
- ; CHECK: $x0 = COPY [[PTRTOINT]](s64)
- ; CHECK: [[LOAD5:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
- ; CHECK: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[LOAD5]](<2 x s32>)
- ; CHECK: $x0 = COPY [[BITCAST]](s64)
- ; CHECK: [[LOAD6:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128))
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[LOAD6]](s128)
- ; CHECK: $x0 = COPY [[TRUNC]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASSERT_ZEXT]](s8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD2]](s16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT2]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; CHECK-NEXT: $x0 = COPY [[LOAD3]](s64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load (p0))
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD4]](p0)
+ ; CHECK-NEXT: $x0 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[LOAD5]](<2 x s32>)
+ ; CHECK-NEXT: $x0 = COPY [[BITCAST]](s64)
+ ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128))
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[LOAD6]](s128)
+ ; CHECK-NEXT: $x0 = COPY [[TRUNC]](s64)
%0:_(p0) = COPY $x0
%1:_(s1) = G_LOAD %0(p0) :: (load (s1))
%2:_(s32) = G_ANYEXT %1(s1)
@@ -63,23 +63,23 @@ body: |
; CHECK-LABEL: name: test_store
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND1]](s32)
- ; CHECK: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8))
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
- ; CHECK: G_STORE [[TRUNC1]](s8), [[COPY]](p0) :: (store (s8))
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; CHECK: G_STORE [[TRUNC2]](s16), [[COPY]](p0) :: (store (s16))
- ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32))
- ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK: G_STORE [[PTRTOINT]](s64), [[COPY]](p0) :: (store (s64))
- ; CHECK: G_STORE [[COPY]](p0), [[COPY]](p0) :: (store (p0))
- ; CHECK: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[PTRTOINT1]](s64), [[PTRTOINT1]](s64)
- ; CHECK: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128))
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND1]](s32)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8))
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: G_STORE [[TRUNC1]](s8), [[COPY]](p0) :: (store (s8))
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[COPY]](p0) :: (store (s16))
+ ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32))
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: G_STORE [[PTRTOINT]](s64), [[COPY]](p0) :: (store (s64))
+ ; CHECK-NEXT: G_STORE [[COPY]](p0), [[COPY]](p0) :: (store (p0))
+ ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[PTRTOINT1]](s64), [[PTRTOINT1]](s64)
+ ; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128))
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(s1) = G_TRUNC %1(s32)
@@ -107,10 +107,11 @@ body: |
; CHECK-LABEL: name: store_4xi16
; CHECK: liveins: $d0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[COPY]](<4 x s16>), [[COPY1]](p0) :: (store (<4 x s16>))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[COPY]](<4 x s16>), [[COPY1]](p0) :: (store (<4 x s16>))
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<4 x s16>) = COPY $d0
%1:_(p0) = COPY $x0
G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>))
@@ -128,10 +129,11 @@ body: |
; CHECK-LABEL: name: store_4xi32
; CHECK: liveins: $q0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[COPY]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[COPY]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>))
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<4 x s32>) = COPY $q0
%1:_(p0) = COPY $x0
G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>))
@@ -149,10 +151,11 @@ body: |
; CHECK-LABEL: name: store_8xi16
; CHECK: liveins: $q0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[COPY]](<8 x s16>), [[COPY1]](p0) :: (store (<8 x s16>))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[COPY]](<8 x s16>), [[COPY1]](p0) :: (store (<8 x s16>))
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<8 x s16>) = COPY $q0
%1:_(p0) = COPY $x0
G_STORE %0(<8 x s16>), %1(p0) :: (store (<8 x s16>))
@@ -170,10 +173,11 @@ body: |
; CHECK-LABEL: name: store_16xi8
; CHECK: liveins: $q0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[COPY]](<16 x s8>), [[COPY1]](p0) :: (store (<16 x s8>))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[COPY]](<16 x s8>), [[COPY1]](p0) :: (store (<16 x s8>))
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<16 x s8>) = COPY $q0
%1:_(p0) = COPY $x0
G_STORE %0(<16 x s8>), %1(p0) :: (store (<16 x s8>))
@@ -191,10 +195,11 @@ body: |
; CHECK-LABEL: name: load_4xi16
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<4 x s16>))
- ; CHECK: $d0 = COPY [[LOAD]](<4 x s16>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<4 x s16>))
+ ; CHECK-NEXT: $d0 = COPY [[LOAD]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(p0) = COPY $x0
%1:_(<4 x s16>) = G_LOAD %0(p0) :: (load (<4 x s16>))
$d0 = COPY %1(<4 x s16>)
@@ -212,10 +217,11 @@ body: |
; CHECK-LABEL: name: load_4xi32
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))
- ; CHECK: $q0 = COPY [[LOAD]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))
+ ; CHECK-NEXT: $q0 = COPY [[LOAD]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(p0) = COPY $x0
%1:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
$q0 = COPY %1(<4 x s32>)
@@ -233,10 +239,11 @@ body: |
; CHECK-LABEL: name: load_8xi16
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))
- ; CHECK: $q0 = COPY [[LOAD]](<8 x s16>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))
+ ; CHECK-NEXT: $q0 = COPY [[LOAD]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(p0) = COPY $x0
%1:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
$q0 = COPY %1(<8 x s16>)
@@ -254,10 +261,11 @@ body: |
; CHECK-LABEL: name: load_16xi8
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))
- ; CHECK: $q0 = COPY [[LOAD]](<16 x s8>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))
+ ; CHECK-NEXT: $q0 = COPY [[LOAD]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(p0) = COPY $x0
%1:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
$q0 = COPY %1(<16 x s8>)
@@ -274,10 +282,11 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_8xi8
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<8 x s8>))
- ; CHECK: $d0 = COPY [[LOAD]](<8 x s8>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<8 x s8>))
+ ; CHECK-NEXT: $d0 = COPY [[LOAD]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(p0) = COPY $x0
%1:_(<8 x s8>) = G_LOAD %0(p0) :: (load (<8 x s8>))
$d0 = COPY %1(<8 x s8>)
@@ -294,10 +303,11 @@ body: |
liveins: $x0, $d0
; CHECK-LABEL: name: store_8xi8
; CHECK: liveins: $x0, $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK: G_STORE [[COPY1]](<8 x s8>), [[COPY]](p0) :: (store (<8 x s8>))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: G_STORE [[COPY1]](<8 x s8>), [[COPY]](p0) :: (store (<8 x s8>))
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(<8 x s8>) = COPY $d0
G_STORE %1(<8 x s8>), %0(p0) :: (store (<8 x s8>))
@@ -313,15 +323,16 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_32xs8
; CHECK: liveins: $x0
- ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: G_STORE [[BUILD_VECTOR]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[BUILD_VECTOR1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%val:_(<32 x s8>) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0
G_STORE %val(<32 x s8>), %ptr(p0) :: (store (<32 x s8>))
@@ -337,15 +348,16 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_16xs16
; CHECK: liveins: $x0
- ; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: G_STORE [[BUILD_VECTOR]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[BUILD_VECTOR1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%val:_(<16 x s16>) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0
G_STORE %val(<16 x s16>), %ptr(p0) :: (store (<16 x s16>))
@@ -361,15 +373,16 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_8xs32
; CHECK: liveins: $x0
- ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: G_STORE [[BUILD_VECTOR]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[BUILD_VECTOR1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%val:_(<8 x s32>) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0
G_STORE %val(<8 x s32>), %ptr(p0) :: (store (<8 x s32>))
@@ -385,13 +398,14 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_4xs64
; CHECK: liveins: $x0
- ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%val:_(<4 x s64>) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0
G_STORE %val(<4 x s64>), %ptr(p0) :: (store (<4 x s64>))
@@ -407,15 +421,16 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_32xs8
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD %ptr(p0) :: (load (<16 x s8>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD]](p0) :: (load (<16 x s8>) from unknown-address + 16)
- ; CHECK: G_STORE [[LOAD]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[LOAD1]](<16 x s8>), [[PTR_ADD1]](p0) :: (store (<16 x s8>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD %ptr(p0) :: (load (<16 x s8>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD]](p0) :: (load (<16 x s8>) from unknown-address + 16)
+ ; CHECK-NEXT: G_STORE [[LOAD]](<16 x s8>), %ptr(p0) :: (store (<16 x s8>), align 32)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](<16 x s8>), [[PTR_ADD1]](p0) :: (store (<16 x s8>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<32 x s8>) = G_LOAD %ptr(p0) :: (load (<32 x s8>))
G_STORE %val(<32 x s8>), %ptr(p0) :: (store (<32 x s8>))
@@ -431,15 +446,16 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_16xs16
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD %ptr(p0) :: (load (<8 x s16>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<8 x s16>) from unknown-address + 16)
- ; CHECK: G_STORE [[LOAD]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[LOAD1]](<8 x s16>), [[PTR_ADD1]](p0) :: (store (<8 x s16>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD %ptr(p0) :: (load (<8 x s16>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<8 x s16>) from unknown-address + 16)
+ ; CHECK-NEXT: G_STORE [[LOAD]](<8 x s16>), %ptr(p0) :: (store (<8 x s16>), align 32)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](<8 x s16>), [[PTR_ADD1]](p0) :: (store (<8 x s16>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<16 x s16>) = G_LOAD %ptr(p0) :: (load (<16 x s16>))
G_STORE %val(<16 x s16>), %ptr(p0) :: (store (<16 x s16>))
@@ -455,15 +471,16 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_8xs32
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD %ptr(p0) :: (load (<4 x s32>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p0) :: (load (<4 x s32>) from unknown-address + 16)
- ; CHECK: G_STORE [[LOAD]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[LOAD1]](<4 x s32>), [[PTR_ADD1]](p0) :: (store (<4 x s32>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD %ptr(p0) :: (load (<4 x s32>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p0) :: (load (<4 x s32>) from unknown-address + 16)
+ ; CHECK-NEXT: G_STORE [[LOAD]](<4 x s32>), %ptr(p0) :: (store (<4 x s32>), align 32)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](<4 x s32>), [[PTR_ADD1]](p0) :: (store (<4 x s32>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<8 x s32>) = G_LOAD %ptr(p0) :: (load (<8 x s32>))
G_STORE %val(<8 x s32>), %ptr(p0) :: (store (<8 x s32>))
@@ -479,15 +496,16 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_4xs64
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load (<2 x s64>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK: G_STORE [[LOAD]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[LOAD1]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr(p0) :: (load (<2 x s64>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
+ ; CHECK-NEXT: G_STORE [[LOAD]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 32)
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[LOAD1]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 16)
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<4 x s64>) = G_LOAD %ptr(p0) :: (load (<4 x s64>))
G_STORE %val(<4 x s64>), %ptr(p0) :: (store (<4 x s64>))
@@ -501,13 +519,13 @@ body: |
; CHECK-LABEL: name: test_trunc_store
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: %val64:_(s64) = COPY $x2
- ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s8))
- ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16))
- ; CHECK: G_STORE %val64(s64), [[COPY]](p0) :: (store (s8))
- ; CHECK: G_STORE %val64(s64), [[COPY]](p0) :: (store (s16))
- ; CHECK: G_STORE %val64(s64), [[COPY]](p0) :: (store (s32))
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: %val64:_(s64) = COPY $x2
+ ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s8))
+ ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16))
+ ; CHECK-NEXT: G_STORE %val64(s64), [[COPY]](p0) :: (store (s8))
+ ; CHECK-NEXT: G_STORE %val64(s64), [[COPY]](p0) :: (store (s16))
+ ; CHECK-NEXT: G_STORE %val64(s64), [[COPY]](p0) :: (store (s32))
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(s8) = G_TRUNC %1(s32)
@@ -526,16 +544,17 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_6xs64
; CHECK: liveins: $x0
- ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>))
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
- ; CHECK: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32)
+ ; CHECK-NEXT: RET_ReallyLR
%val:_(<6 x s64>) = G_IMPLICIT_DEF
%ptr:_(p0) = COPY $x0
G_STORE %val(<6 x s64>), %ptr(p0) :: (store (<6 x s64>), align 16)
@@ -550,14 +569,15 @@ body: |
; CHECK-LABEL: name: store_2xi16
; CHECK: liveins: $s0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $s0
- ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
- ; CHECK: G_STORE [[UV]](s16), [[COPY]](p0) :: (store (s16), align 4)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK: G_STORE [[UV1]](s16), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
+ ; CHECK-NEXT: G_STORE [[UV]](s16), [[COPY]](p0) :: (store (s16), align 4)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: G_STORE [[UV1]](s16), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(<2 x s16>) = COPY $s0
G_STORE %1(<2 x s16>), %0(p0) :: (store (<2 x s16>))
@@ -573,14 +593,15 @@ body: |
; CHECK-LABEL: name: load_2xi16
; CHECK: liveins: $s0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16)
- ; CHECK: $s0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16)
+ ; CHECK-NEXT: $s0 = COPY [[BUILD_VECTOR]](<2 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1(<2 x s16>) = G_LOAD %0(p0) :: (load (<2 x s16>))
$s0 = COPY %1:_(<2 x s16>)
@@ -595,31 +616,32 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_store_s88_s88_mem_size
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 8, align 8)
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 10, align 2)
- ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](s32)
- ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C3]](s64)
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD]]
- ; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR]], [[C]]
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[OR1]](s64)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64)
- ; CHECK: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 16)
- ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
- ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
- ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C2]](s64)
- ; CHECK: G_STORE [[TRUNC]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
- ; CHECK: G_STORE [[LSHR]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 8, align 8)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 10, align 2)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C3]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR]], [[C]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[OR1]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64)
+ ; CHECK-NEXT: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 16)
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C2]](s64)
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
+ ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%load:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
G_STORE %load(s88), %ptr(p0) :: (store (s88))
@@ -633,10 +655,11 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_store_s88_s64_mem_size
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64))
- ; CHECK: G_STORE [[LOAD]](s64), %ptr(p0) :: (store (s64))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64))
+ ; CHECK-NEXT: G_STORE [[LOAD]](s64), %ptr(p0) :: (store (s64))
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%load:_(s88) = G_LOAD %ptr(p0) :: (load (s64))
G_STORE %load(s88), %ptr(p0) :: (store (s64))
@@ -652,14 +675,15 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_s1
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
- ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASSERT_ZEXT]](s8)
- ; CHECK: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK: $x0 = COPY %ext(s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASSERT_ZEXT]](s8)
+ ; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%ptr:_(p0) = COPY $x0
%load:_(s1) = G_LOAD %ptr(p0) :: (load (s1))
%ext:_(s64) = G_ZEXT %load
@@ -676,35 +700,36 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_store_6xp0
; CHECK: liveins: $x0
- ; CHECK: %ptr:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD %ptr(p0) :: (load (p0), align 64)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD]](p0) :: (load (p0) from unknown-address + 8)
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
- ; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load (p0) from unknown-address + 16, align 16)
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C2]](s64)
- ; CHECK: [[LOAD3:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD2]](p0) :: (load (p0) from unknown-address + 24)
- ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
- ; CHECK: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD3]](p0) :: (load (p0) from unknown-address + 32, align 32)
- ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
- ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C4]](s64)
- ; CHECK: [[LOAD5:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD4]](p0) :: (load (p0) from unknown-address + 40)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD]](p0), [[LOAD1]](p0)
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD2]](p0), [[LOAD3]](p0)
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD4]](p0), [[LOAD5]](p0)
- ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR]](<2 x p0>)
- ; CHECK: G_STORE [[BITCAST]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 64)
- ; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
- ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR1]](<2 x p0>)
- ; CHECK: G_STORE [[BITCAST1]](<2 x s64>), [[PTR_ADD5]](p0) :: (store (<2 x s64>) into unknown-address + 16)
- ; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
- ; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR2]](<2 x p0>)
- ; CHECK: G_STORE [[BITCAST2]](<2 x s64>), [[PTR_ADD6]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD %ptr(p0) :: (load (p0), align 64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD]](p0) :: (load (p0) from unknown-address + 8)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load (p0) from unknown-address + 16, align 16)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C2]](s64)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD2]](p0) :: (load (p0) from unknown-address + 24)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+ ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD3]](p0) :: (load (p0) from unknown-address + 32, align 32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
+ ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C4]](s64)
+ ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD4]](p0) :: (load (p0) from unknown-address + 40)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD]](p0), [[LOAD1]](p0)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD2]](p0), [[LOAD3]](p0)
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[LOAD4]](p0), [[LOAD5]](p0)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>), align 64)
+ ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR1]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST1]](<2 x s64>), [[PTR_ADD5]](p0) :: (store (<2 x s64>) into unknown-address + 16)
+ ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[BUILD_VECTOR2]](<2 x p0>)
+ ; CHECK-NEXT: G_STORE [[BITCAST2]](<2 x s64>), [[PTR_ADD6]](p0) :: (store (<2 x s64>) into unknown-address + 32, align 32)
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%val:_(<6 x p0>) = G_LOAD %ptr(p0) :: (load (<6 x p0>))
G_STORE %val(<6 x p0>), %ptr(p0) :: (store (<6 x p0>))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
index ad96fabeb11bc..9c682cd50e273 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
@@ -40,36 +40,42 @@ frameInfo:
body: |
; CHECK-LABEL: name: snork
; CHECK: bb.0.bb:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
- ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK: bb.1.bb1:
- ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0
- ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI %20(s16), %bb.2, [[DEF1]](s16), %bb.0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[PHI1]](s16)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.3
- ; CHECK: bb.2.bb3:
- ; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[C1]](s64)
- ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PHI]](p0) :: (load (s16) from %ir.lsr.iv)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C2]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from %ir.tmp5)
- ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]]
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PHI]], [[C1]](s64)
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
- ; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.3
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.3.bb10:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb1:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI %20(s16), %bb.2, [[DEF1]](s16), %bb.0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[PHI1]](s16)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb3:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[C1]](s64)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PHI]](p0) :: (load (s16) from %ir.lsr.iv)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C2]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from %ir.tmp5)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]]
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PHI]], [[C1]](s64)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC1]](s1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb10:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1.bb:
%3:_(s64) = G_CONSTANT i64 0
%2:_(p0) = G_INTTOPTR %3(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 6d402463abe33..10a85292c2f21 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -24,32 +24,38 @@ liveins:
body: |
; CHECK-LABEL: name: legalize_phi
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK: G_BR %bb.3
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
- ; CHECK: bb.3:
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; CHECK: $w0 = COPY [[AND]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
; Test that we insert legalization artifacts(Truncs here) into the correct BBs
; while legalizing the G_PHI to s16.
@@ -106,20 +112,24 @@ liveins:
body: |
; CHECK-LABEL: name: legalize_phi_ptr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w2, $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
- ; CHECK: $x0 = COPY [[PHI]](p0)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w2, $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
+ ; CHECK-NEXT: $x0 = COPY [[PHI]](p0)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
bb.1:
successors: %bb.2, %bb.3
@@ -165,32 +175,38 @@ liveins:
body: |
; CHECK-LABEL: name: legalize_phi_empty
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
- ; CHECK: G_BR %bb.3
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK: bb.3:
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; CHECK: $w0 = COPY [[AND]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $w0
@@ -248,27 +264,31 @@ liveins:
body: |
; CHECK-LABEL: name: legalize_phi_loop
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %13(s16), %bb.1
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: bb.2:
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
- ; CHECK: $w0 = COPY [[AND1]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %13(s16), %bb.1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x80000000)
liveins: $w0
@@ -311,22 +331,26 @@ liveins:
body: |
; CHECK-LABEL: name: legalize_phi_cycle
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, [[PHI]](s16), %bb.1
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: bb.2:
- ; CHECK: $w0 = COPY [[AND]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, [[PHI]](s16), %bb.1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x80000000)
liveins: $w0
@@ -377,38 +401,44 @@ liveins:
body: |
; CHECK-LABEL: name: legalize_phi_same_bb
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
- ; CHECK: G_BR %bb.3
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 42
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK: bb.3:
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC3]](s16), %bb.2
- ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[C3]](s16), %bb.2
- ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
- ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: $w0 = COPY [[ADD2]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 42
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC3]](s16), %bb.2
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[C3]](s16), %bb.2
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $w0
@@ -479,40 +509,44 @@ liveins:
body: |
; CHECK-LABEL: name: legalize_phi_
diff _bb
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.0, %21(s16), %bb.1
- ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
- ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
- ; CHECK: G_BRCOND [[TRUNC3]](s1), %bb.2
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.2:
- ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[PHI]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
- ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C6]]
- ; CHECK: $w0 = COPY [[AND1]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.0, %21(s16), %bb.1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
+ ; CHECK-NEXT: G_BRCOND [[TRUNC3]](s1), %bb.2
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[PHI]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C6]]
+ ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $w0, $w1
@@ -562,20 +596,22 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: legalize_phi_check_insertpt
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[DEF]](s64), %bb.0
- ; CHECK: [[PHI1:%[0-9]+]]:_(s64) = G_PHI [[DEF]](s64), %bb.0
- ; CHECK: [[PHI2:%[0-9]+]]:_(s64) = G_PHI [[COPY]](s64), %bb.0
- ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[PHI]](s64), [[PHI1]](s64)
- ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store (s128))
- ; CHECK: G_STORE [[PHI2]](s64), [[COPY1]](p0) :: (store (s64))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[DEF]](s64), %bb.0
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s64) = G_PHI [[DEF]](s64), %bb.0
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s64) = G_PHI [[COPY]](s64), %bb.0
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[PHI]](s64), [[PHI1]](s64)
+ ; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store (s128))
+ ; CHECK-NEXT: G_STORE [[PHI2]](s64), [[COPY1]](p0) :: (store (s64))
+ ; CHECK-NEXT: RET_ReallyLR
; Check that the G_MERGE here gets inserted after all the PHIs.
bb.0:
successors: %bb.1(0x40000000)
@@ -600,14 +636,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: legalize_phi_vector
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $q0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: [[PHI:%[0-9]+]]:_(<16 x s8>) = G_PHI [[COPY]](<16 x s8>), %bb.0
- ; CHECK: $q0 = COPY [[PHI]](<16 x s8>)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $q0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<16 x s8>) = G_PHI [[COPY]](<16 x s8>), %bb.0
+ ; CHECK-NEXT: $q0 = COPY [[PHI]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.1
liveins: $q0, $x1
@@ -627,22 +665,28 @@ liveins:
body: |
; CHECK-LABEL: name: s88
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: %cond:_(s1) = G_IMPLICIT_DEF
- ; CHECK: G_BRCOND %cond(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: G_BR %bb.3
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: bb.3:
- ; CHECK: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[DEF]](s64), %bb.1, [[DEF1]](s64), %bb.2
- ; CHECK: $x0 = COPY [[PHI]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond:_(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[DEF]](s64), %bb.1, [[DEF1]](s64), %bb.2
+ ; CHECK-NEXT: $x0 = COPY [[PHI]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $x0
@@ -669,29 +713,33 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: v4s64
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1
- ; CHECK: %ptr1:_(p0) = COPY $x1
- ; CHECK: %ptr2:_(p0) = COPY $x0
- ; CHECK: %cond:_(s1) = G_IMPLICIT_DEF
- ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK: G_BRCOND %cond(s1), %bb.2
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C1]](s64)
- ; CHECK: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:_(<2 x s64>) = G_PHI [[LOAD2]](<2 x s64>), %bb.1, [[LOAD]](<2 x s64>), %bb.0
- ; CHECK: [[PHI1:%[0-9]+]]:_(<2 x s64>) = G_PHI [[LOAD3]](<2 x s64>), %bb.1, [[LOAD1]](<2 x s64>), %bb.0
- ; CHECK: $q0 = COPY [[PHI]](<2 x s64>)
- ; CHECK: $q1 = COPY [[PHI1]](<2 x s64>)
- ; CHECK: RET_ReallyLR implicit $q0, implicit $q1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr1:_(p0) = COPY $x1
+ ; CHECK-NEXT: %ptr2:_(p0) = COPY $x0
+ ; CHECK-NEXT: %cond:_(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.2
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C1]](s64)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x s64>) = G_PHI [[LOAD2]](<2 x s64>), %bb.1, [[LOAD]](<2 x s64>), %bb.0
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s64>) = G_PHI [[LOAD3]](<2 x s64>), %bb.1, [[LOAD1]](<2 x s64>), %bb.0
+ ; CHECK-NEXT: $q0 = COPY [[PHI]](<2 x s64>)
+ ; CHECK-NEXT: $q1 = COPY [[PHI1]](<2 x s64>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1
@@ -718,23 +766,27 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: v8s32
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1
- ; CHECK: %cond:_(s1) = G_IMPLICIT_DEF
- ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
- ; CHECK: G_BRCOND %cond(s1), %bb.2
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF1]](s32), [[DEF1]](s32), [[DEF1]](s32), [[DEF1]](s32)
- ; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:_(<4 x s32>) = G_PHI [[BUILD_VECTOR1]](<4 x s32>), %bb.1, [[BUILD_VECTOR]](<4 x s32>), %bb.0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), [[C]](s64)
- ; CHECK: $w0 = COPY %extract(s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond:_(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.2
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF1]](s32), [[DEF1]](s32), [[DEF1]](s32), [[DEF1]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x s32>) = G_PHI [[BUILD_VECTOR1]](<4 x s32>), %bb.1, [[BUILD_VECTOR]](<4 x s32>), %bb.0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), [[C]](s64)
+ ; CHECK-NEXT: $w0 = COPY %extract(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1
@@ -758,23 +810,27 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: v16s16
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1
- ; CHECK: %cond:_(s1) = G_IMPLICIT_DEF
- ; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK: G_BRCOND %cond(s1), %bb.2
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16)
- ; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:_(<8 x s16>) = G_PHI [[BUILD_VECTOR1]](<8 x s16>), %bb.1, [[BUILD_VECTOR]](<8 x s16>), %bb.0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), [[C]](s64)
- ; CHECK: $h0 = COPY %extract(s16)
- ; CHECK: RET_ReallyLR implicit $h0
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond:_(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.2
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16), [[DEF1]](s16)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<8 x s16>) = G_PHI [[BUILD_VECTOR1]](<8 x s16>), %bb.1, [[BUILD_VECTOR]](<8 x s16>), %bb.0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), [[C]](s64)
+ ; CHECK-NEXT: $h0 = COPY %extract(s16)
+ ; CHECK-NEXT: RET_ReallyLR implicit $h0
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1
@@ -798,22 +854,26 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: v32s8
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1
- ; CHECK: %cond:_(s1) = G_IMPLICIT_DEF
- ; CHECK: %val_1:_(<32 x s8>) = G_IMPLICIT_DEF
- ; CHECK: G_BRCOND %cond(s1), %bb.2
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %val_2:_(<32 x s8>) = G_IMPLICIT_DEF
- ; CHECK: bb.2:
- ; CHECK: %phi:_(<32 x s8>) = G_PHI %val_2(<32 x s8>), %bb.1, %val_1(<32 x s8>), %bb.0
- ; CHECK: %one:_(s8) = G_CONSTANT i8 1
- ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT %one(s8)
- ; CHECK: %extract:_(s8) = G_EXTRACT_VECTOR_ELT %phi(<32 x s8>), [[SEXT]](s64)
- ; CHECK: $b0 = COPY %extract(s8)
- ; CHECK: RET_ReallyLR implicit $b0
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond:_(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: %val_1:_(<32 x s8>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.2
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %val_2:_(<32 x s8>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %phi:_(<32 x s8>) = G_PHI %val_2(<32 x s8>), %bb.1, %val_1(<32 x s8>), %bb.0
+ ; CHECK-NEXT: %one:_(s8) = G_CONSTANT i8 1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT %one(s8)
+ ; CHECK-NEXT: %extract:_(s8) = G_EXTRACT_VECTOR_ELT %phi(<32 x s8>), [[SEXT]](s64)
+ ; CHECK-NEXT: $b0 = COPY %extract(s8)
+ ; CHECK-NEXT: RET_ReallyLR implicit $b0
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1
@@ -837,33 +897,37 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: v4p0
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1
- ; CHECK: %ptr1:_(p0) = COPY $x1
- ; CHECK: %ptr2:_(p0) = COPY $x0
- ; CHECK: %cond:_(s1) = G_IMPLICIT_DEF
- ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
- ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
- ; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
- ; CHECK: G_BRCOND %cond(s1), %bb.2
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
- ; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C1]](s64)
- ; CHECK: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x s64>)
- ; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST2]](<2 x p0>), %bb.1, [[BITCAST]](<2 x p0>), %bb.0
- ; CHECK: [[PHI1:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST3]](<2 x p0>), %bb.1, [[BITCAST1]](<2 x p0>), %bb.0
- ; CHECK: $q0 = COPY [[PHI]](<2 x p0>)
- ; CHECK: $q1 = COPY [[PHI1]](<2 x p0>)
- ; CHECK: RET_ReallyLR implicit $q0, implicit $q1
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr1:_(p0) = COPY $x1
+ ; CHECK-NEXT: %ptr2:_(p0) = COPY $x0
+ ; CHECK-NEXT: %cond:_(s1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr1(p0) :: (load (<2 x s64>), align 32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.2
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(<2 x s64>) = G_LOAD %ptr2(p0) :: (load (<2 x s64>), align 32)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD2]](<2 x s64>)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+ ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr2, [[C1]](s64)
+ ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD1]](p0) :: (load (<2 x s64>) from unknown-address + 16)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD3]](<2 x s64>)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST2]](<2 x p0>), %bb.1, [[BITCAST]](<2 x p0>), %bb.0
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x p0>) = G_PHI [[BITCAST3]](<2 x p0>), %bb.1, [[BITCAST1]](<2 x p0>), %bb.0
+ ; CHECK-NEXT: $q0 = COPY [[PHI]](<2 x p0>)
+ ; CHECK-NEXT: $q1 = COPY [[PHI1]](<2 x p0>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
index 3825827796dd4..bed3f33c7b4af 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
@@ -7,17 +7,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_sadde_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], %carry_in
- ; CHECK: %19:_(s64), %carry_out:_(s1) = G_SADDE [[COPY1]], [[COPY3]], [[UADDE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDE]](s64)
- ; CHECK: $x1 = COPY %19(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], %carry_in
+ ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_SADDE [[COPY1]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: $x1 = COPY %19(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -40,19 +40,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_sadde_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], %carry_in
- ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
- ; CHECK: %24:_(s64), %carry_out:_(s1) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE3]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDE]](s64)
- ; CHECK: $x1 = COPY [[UADDE2]](s64)
- ; CHECK: $x2 = COPY %24(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], %carry_in
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
+ ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE3]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
+ ; CHECK-NEXT: $x2 = COPY %24(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -76,20 +76,20 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: widen_scalar_sadde_s8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 8
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
- ; CHECK: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY %add_ext(s64)
- ; CHECK: $x1 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 8
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY %add_ext(s64)
+ ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -109,13 +109,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_sadde_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: %add:_(s32), %carry_out:_(s1) = G_SADDE %lhs, %rhs, %carry_in
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %add(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_SADDE %lhs, %rhs, %carry_in
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %add(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
index 3cca9ed58b58e..7d5cb7ffa6837 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
@@ -7,15 +7,15 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_saddo_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK: %17:_(s64), %carry_out:_(s1) = G_SADDE [[COPY1]], [[COPY3]], [[UADDO1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY %17(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_SADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY %17(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -36,17 +36,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_saddo_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
- ; CHECK: %22:_(s64), %carry_out:_(s1) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY [[UADDE]](s64)
- ; CHECK: $x2 = COPY %22(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
+ ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: $x2 = COPY %22(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -68,18 +68,18 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_saddo_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 8
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY [[ANYEXT]](s64)
- ; CHECK: $x1 = COPY [[ANYEXT1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 8
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@@ -97,11 +97,11 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_saddo_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: %add:_(s32), %carry_out:_(s1) = G_SADDO %lhs, %rhs
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %add(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_SADDO %lhs, %rhs
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %add(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%add:_(s32), %carry_out:_(s1) = G_SADDO %lhs, %rhs
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
index cbde294d6dfeb..5fbc1b256b62d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
@@ -11,23 +11,24 @@ body: |
; CHECK-LABEL: name: v2s64
; CHECK: liveins: $q0, $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[BUILD_VECTOR]]
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s64>)
- ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s64>)
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
- ; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR]], [[BUILD_VECTOR2]]
- ; CHECK: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[COPY1]], [[ASHR]]
- ; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[COPY]], [[XOR]]
- ; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
- ; CHECK: $q0 = COPY [[OR]](<2 x s64>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s64>)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s64>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR]], [[BUILD_VECTOR2]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[COPY1]], [[ASHR]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[COPY]], [[XOR]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
%3:_(s64) = G_CONSTANT i64 0
@@ -48,23 +49,24 @@ body: |
; CHECK-LABEL: name: v2s32
; CHECK: liveins: $d0, $d1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[BUILD_VECTOR]]
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s32>)
- ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s32>)
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(<2 x s32>) = G_XOR [[ASHR]], [[BUILD_VECTOR2]]
- ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[ASHR]]
- ; CHECK: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[XOR]]
- ; CHECK: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
- ; CHECK: $d0 = COPY [[OR]](<2 x s32>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s32>)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s32>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s32>) = G_XOR [[ASHR]], [[BUILD_VECTOR2]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[ASHR]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[XOR]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: $d0 = COPY [[OR]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
%3:_(s32) = G_CONSTANT i32 0
@@ -85,23 +87,24 @@ body: |
; CHECK-LABEL: name: v16s8
; CHECK: liveins: $q0, $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
- ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
- ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[BUILD_VECTOR]]
- ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8)
- ; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<16 x s8>)
- ; CHECK: [[ASHR:%[0-9]+]]:_(<16 x s8>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<16 x s8>)
- ; CHECK: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8)
- ; CHECK: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[ASHR]], [[BUILD_VECTOR2]]
- ; CHECK: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY1]], [[ASHR]]
- ; CHECK: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[XOR]]
- ; CHECK: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[AND]], [[AND1]]
- ; CHECK: $q0 = COPY [[OR]](<16 x s8>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<16 x s8>)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<16 x s8>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<16 x s8>)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[ASHR]], [[BUILD_VECTOR2]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY1]], [[ASHR]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[XOR]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
%3:_(s8) = G_CONSTANT i8 0
@@ -124,25 +127,26 @@ body: |
; CHECK-LABEL: name: scalar_mask
; CHECK: liveins: $q0, $w0
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4100
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
- ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT_INREG]](s32), [[C2]](s64)
- ; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
- ; CHECK: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
- ; CHECK: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND]], [[AND1]]
- ; CHECK: $q0 = COPY [[OR]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4100
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT_INREG]](s32), [[C2]](s64)
+ ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(s32) = COPY $w0
%1:_(<4 x s32>) = COPY $q0
%2:_(s32) = G_CONSTANT i32 4100
@@ -163,14 +167,15 @@ body: |
; CHECK-LABEL: name: s88
; CHECK: liveins: $w0, $w1, $x0
- ; CHECK: %a:_(s32) = COPY $w0
- ; CHECK: %b:_(s32) = COPY $w1
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %a(s32), %b
- ; CHECK: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT %cmp(s1), [[DEF]], [[DEF]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s32) = COPY $w0
+ ; CHECK-NEXT: %b:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %a(s32), %b
+ ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT %cmp(s1), [[DEF]], [[DEF]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w1
%cmp:_(s1) = G_ICMP intpred(sgt), %a(s32), %b
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index be946f7a5dae4..f2733fcba4766 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -5,41 +5,43 @@ name: test_simple
body: |
; CHECK-LABEL: name: test_simple
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
- ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
- ; CHECK: $x0 = COPY [[PTRTOINT]](s64)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: bb.1:
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
- ; CHECK: $w0 = COPY [[SELECT1]](s32)
- ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
- ; CHECK: $w0 = COPY [[SELECT2]](s32)
- ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
- ; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
- ; CHECK: $x0 = COPY [[SELECT4]](s64)
- ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
- ; CHECK: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[BITCAST]](<2 x s32>)
- ; CHECK: $x0 = COPY [[BITCAST1]](s64)
- ; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[SELECT3]](s32)
- ; CHECK: $w0 = COPY [[BITCAST2]](<2 x s16>)
- ; CHECK: [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[TRUNC1]](s32)
- ; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST3]](<4 x s8>)
- ; CHECK: $w0 = COPY [[BITCAST4]](s32)
- ; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[TRUNC1]](s32)
- ; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST5]](<2 x s16>)
- ; CHECK: $w0 = COPY [[BITCAST6]](s32)
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
+ ; CHECK-NEXT: $x0 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT1]](s32)
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT2]](s32)
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT4]](s64)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[BITCAST]](<2 x s32>)
+ ; CHECK-NEXT: $x0 = COPY [[BITCAST1]](s64)
+ ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[SELECT3]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[BITCAST2]](<2 x s16>)
+ ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[TRUNC1]](s32)
+ ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST3]](<4 x s8>)
+ ; CHECK-NEXT: $w0 = COPY [[BITCAST4]](s32)
+ ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[TRUNC1]](s32)
+ ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST5]](<2 x s16>)
+ ; CHECK-NEXT: $w0 = COPY [[BITCAST6]](s32)
bb.0.entry:
successors: %bb.1(0x80000000)
@@ -87,11 +89,11 @@ body: |
; CHECK-LABEL: name: bitcast128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
- ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[MV]](s128)
- ; CHECK: $q0 = COPY [[BITCAST]](<2 x s64>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[MV]](s128)
+ ; CHECK-NEXT: $q0 = COPY [[BITCAST]](<2 x s64>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%3:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
@@ -108,8 +110,8 @@ body: |
; CHECK-LABEL: name: testExtOfCopyOfTrunc
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: $x0 = COPY [[COPY]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64)
%2:_(s1) = COPY %1(s1)
@@ -126,8 +128,8 @@ body: |
; CHECK-LABEL: name: testExtOf2CopyOfTrunc
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: $x0 = COPY [[COPY]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64)
%2:_(s1) = COPY %1(s1)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
index 841879f18bf34..bf38a206f4b40 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
@@ -7,17 +7,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_ssube_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY2]], %carry_in
- ; CHECK: %19:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBE]](s64)
- ; CHECK: $x1 = COPY %19(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY2]], %carry_in
+ ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: $x1 = COPY %19(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -40,19 +40,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_ssube_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY1]], %carry_in
- ; CHECK: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
- ; CHECK: %24:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE3]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBE]](s64)
- ; CHECK: $x1 = COPY [[USUBE2]](s64)
- ; CHECK: $x2 = COPY %24(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY1]], %carry_in
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
+ ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE3]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
+ ; CHECK-NEXT: $x2 = COPY %24(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -76,20 +76,20 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: widen_scalar_ssube_s8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 8
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
- ; CHECK: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY %sub_ext(s64)
- ; CHECK: $x1 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 8
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY %sub_ext(s64)
+ ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -109,13 +109,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_ssube_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: %sub:_(s32), %carry_out:_(s1) = G_SSUBE %lhs, %rhs, %carry_in
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %sub(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_SSUBE %lhs, %rhs, %carry_in
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %sub(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
index 973570e49fbb9..86aaa0e1413f7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
@@ -7,15 +7,15 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_ssubo_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
- ; CHECK: %17:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBO1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBO]](s64)
- ; CHECK: $x1 = COPY %17(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
+ ; CHECK-NEXT: $x1 = COPY %17(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -36,17 +36,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_ssubo_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
- ; CHECK: %22:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBO]](s64)
- ; CHECK: $x1 = COPY [[USUBE]](s64)
- ; CHECK: $x2 = COPY %22(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
+ ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: $x2 = COPY %22(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -68,18 +68,18 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_ssubo_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 8
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY [[ANYEXT]](s64)
- ; CHECK: $x1 = COPY [[ANYEXT1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 8
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@@ -97,11 +97,11 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_ssubo_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: %sub:_(s32), %carry_out:_(s1) = G_SSUBO %lhs, %rhs
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %sub(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_SSUBO %lhs, %rhs
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %sub(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%sub:_(s32), %carry_out:_(s1) = G_SSUBO %lhs, %rhs
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index f6603a444a5f8..ddc6b8bad3389 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -7,13 +7,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_sub_big
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
- ; CHECK: $x0 = COPY [[USUBO]](s64)
- ; CHECK: $x1 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+ ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -32,15 +32,15 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_sub_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
- ; CHECK: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
- ; CHECK: $x0 = COPY [[USUBO]](s64)
- ; CHECK: $x1 = COPY [[USUBE]](s64)
- ; CHECK: $x2 = COPY [[USUBE2]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: $x2 = COPY [[USUBE2]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -60,12 +60,12 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_sub_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
- ; CHECK: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
index fee7736d629e1..12da25dc909f9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
@@ -13,13 +13,14 @@ body: |
; CHECK-LABEL: name: func
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[UADDO1]](s1), [[C]], [[UADDO]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[UADDO1]](s1), [[C]], [[UADDO]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_UADDSAT %0, %1
@@ -40,13 +41,14 @@ body: |
; CHECK-LABEL: name: func2
; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[UADDO1]](s1), [[C]], [[UADDO]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[UADDO1]](s1), [[C]], [[UADDO]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_UADDSAT %0, %1
@@ -67,19 +69,20 @@ body: |
; CHECK-LABEL: name: func16
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
@@ -103,19 +106,20 @@ body: |
; CHECK-LABEL: name: func8
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
@@ -142,19 +146,20 @@ body: |
; CHECK-LABEL: name: func3
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY2]], [[ADD]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY2]], [[ADD]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s4) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
index a9e870e46c6ee..74fa7256f133f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
@@ -7,17 +7,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_uadde_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], %carry_in
- ; CHECK: %19:_(s64), %carry_out:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDE]](s64)
- ; CHECK: $x1 = COPY %19(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], %carry_in
+ ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: $x1 = COPY %19(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -40,19 +40,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_uadde_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], %carry_in
- ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
- ; CHECK: %24:_(s64), %carry_out:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE3]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDE]](s64)
- ; CHECK: $x1 = COPY [[UADDE2]](s64)
- ; CHECK: $x2 = COPY %24(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], %carry_in
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
+ ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE3]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
+ ; CHECK-NEXT: $x2 = COPY %24(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -76,21 +76,21 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: widen_scalar_uadde_s8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
- ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], %carry_in
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
- ; CHECK: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY %add_ext(s64)
- ; CHECK: $x1 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], %carry_in
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
+ ; CHECK-NEXT: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY %add_ext(s64)
+ ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -110,13 +110,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_uadde_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: %add:_(s32), %carry_out:_(s1) = G_UADDE %lhs, %rhs, %carry_in
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %add(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_UADDE %lhs, %rhs, %carry_in
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %add(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
index 3724e1476a936..c032e16c5396e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
@@ -7,15 +7,15 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_uaddo_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK: %17:_(s64), %carry_out:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY %17(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY %17(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -36,17 +36,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_uaddo_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
- ; CHECK: %22:_(s64), %carry_out:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[UADDO]](s64)
- ; CHECK: $x1 = COPY [[UADDE]](s64)
- ; CHECK: $x2 = COPY %22(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
+ ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
+ ; CHECK-NEXT: $x2 = COPY %22(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -68,19 +68,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_uaddo_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY [[ANYEXT]](s64)
- ; CHECK: $x1 = COPY [[ANYEXT1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@@ -98,11 +98,11 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_uaddo_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: %add:_(s32), %carry_out:_(s1) = G_UADDO %lhs, %rhs
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %add(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: %add:_(s32), %carry_out:_(s1) = G_UADDO %lhs, %rhs
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %add(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%add:_(s32), %carry_out:_(s1) = G_UADDO %lhs, %rhs
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
index a420263790e14..742c0b2599154 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
@@ -13,13 +13,14 @@ body: |
; CHECK-LABEL: name: func
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[USUBO1]](s1), [[C]], [[USUBO]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[USUBO1]](s1), [[C]], [[USUBO]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_USUBSAT %0, %1
@@ -40,13 +41,14 @@ body: |
; CHECK-LABEL: name: func2
; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[USUBO1]](s1), [[C]], [[USUBO]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[USUBO1]](s1), [[C]], [[USUBO]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_USUBSAT %0, %1
@@ -67,19 +69,20 @@ body: |
; CHECK-LABEL: name: func16
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
@@ -103,19 +106,20 @@ body: |
; CHECK-LABEL: name: func8
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
@@ -139,19 +143,20 @@ body: |
; CHECK-LABEL: name: func3
; CHECK: liveins: $w0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
- ; CHECK: $w0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+ ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s4) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
index 91636c5590e27..3e03a3ac3d4a8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
@@ -7,17 +7,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_usube_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY2]], %carry_in
- ; CHECK: %19:_(s64), %carry_out:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBE]](s64)
- ; CHECK: $x1 = COPY %19(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY2]], %carry_in
+ ; CHECK-NEXT: %19:_(s64), %carry_out:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: $x1 = COPY %19(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -40,19 +40,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_usube_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY1]], %carry_in
- ; CHECK: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
- ; CHECK: %24:_(s64), %carry_out:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE3]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBE]](s64)
- ; CHECK: $x1 = COPY [[USUBE2]](s64)
- ; CHECK: $x2 = COPY %24(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY4]](s64)
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY]], [[COPY1]], %carry_in
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
+ ; CHECK-NEXT: %24:_(s64), %carry_out:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE3]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
+ ; CHECK-NEXT: $x2 = COPY %24(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -76,21 +76,21 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: widen_scalar_usube_s8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
- ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], %carry_in
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
- ; CHECK: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY %sub_ext(s64)
- ; CHECK: $x1 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY2]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], %carry_in
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
+ ; CHECK-NEXT: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY %sub_ext(s64)
+ ; CHECK-NEXT: $x1 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -110,13 +110,13 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_usube_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: %sub:_(s32), %carry_out:_(s1) = G_USUBE %lhs, %rhs, %carry_in
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %sub(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w2
+ ; CHECK-NEXT: %carry_in:_(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_USUBE %lhs, %rhs, %carry_in
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %sub(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
index e53f1ef04031e..7037fc2f5c275 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
@@ -7,15 +7,15 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_usubo_s128
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
- ; CHECK: %17:_(s64), %carry_out:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBO]](s64)
- ; CHECK: $x1 = COPY %17(s64)
- ; CHECK: $x2 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: %17:_(s64), %carry_out:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
+ ; CHECK-NEXT: $x1 = COPY %17(s64)
+ ; CHECK-NEXT: $x2 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -36,17 +36,17 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: narrow_scalar_usubo_big_nonpow2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
- ; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
- ; CHECK: %22:_(s64), %carry_out:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
- ; CHECK: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
- ; CHECK: $x0 = COPY [[USUBO]](s64)
- ; CHECK: $x1 = COPY [[USUBE]](s64)
- ; CHECK: $x2 = COPY %22(s64)
- ; CHECK: $x3 = COPY %carry_out_ext(s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
+ ; CHECK-NEXT: %22:_(s64), %carry_out:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
+ ; CHECK-NEXT: $x2 = COPY %22(s64)
+ ; CHECK-NEXT: $x3 = COPY %carry_out_ext(s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
@@ -68,19 +68,19 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_usubo_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
- ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
- ; CHECK: $x0 = COPY [[ANYEXT]](s64)
- ; CHECK: $x1 = COPY [[ANYEXT1]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@@ -98,11 +98,11 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_usubo_32
; CHECK: %lhs:_(s32) = COPY $w0
- ; CHECK: %rhs:_(s32) = COPY $w1
- ; CHECK: %sub:_(s32), %carry_out:_(s1) = G_USUBO %lhs, %rhs
- ; CHECK: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
- ; CHECK: $w0 = COPY %sub(s32)
- ; CHECK: $w1 = COPY %carry_out_ext(s32)
+ ; CHECK-NEXT: %rhs:_(s32) = COPY $w1
+ ; CHECK-NEXT: %sub:_(s32), %carry_out:_(s1) = G_USUBO %lhs, %rhs
+ ; CHECK-NEXT: %carry_out_ext:_(s32) = G_ANYEXT %carry_out(s1)
+ ; CHECK-NEXT: $w0 = COPY %sub(s32)
+ ; CHECK-NEXT: $w1 = COPY %carry_out_ext(s32)
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
%sub:_(s32), %carry_out:_(s1) = G_USUBO %lhs, %rhs
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
index e25e93064f811..37832293b81b5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
@@ -9,33 +9,38 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: zext_trunc_dead_inst_crash
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI %32(s16), %bb.2, [[DEF]](s16), %bb.0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
- ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
- ; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[DEF1]]
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -33
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[C3]]
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C4]]
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[OR]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR1]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 64
- ; CHECK: G_BR %bb.1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI %32(s16), %bb.2, [[DEF]](s16), %bb.0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[DEF1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -33
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[C3]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C4]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[OR]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR1]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 64
+ ; CHECK-NEXT: G_BR %bb.1
bb.1:
%1:_(s8) = G_CONSTANT i8 46
%3:_(s1) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
index 2daaf89d1225d..298c8b749a89a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
@@ -17,33 +17,38 @@ target triple = "arm64-apple-ios5.0.0"
define i32 @foo() {
; CHECK-LABEL: name: foo
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; CHECK: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
- ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
- ; CHECK: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
- ; CHECK: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
- ; CHECK: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.if.then:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
- ; CHECK: G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2)
- ; CHECK: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
- ; CHECK: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1)
- ; CHECK: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
- ; CHECK: G_STORE [[C4]](s32), [[GV4]](p0) :: (store (s32) into @var3)
- ; CHECK: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1)
- ; CHECK: bb.3.if.end:
- ; CHECK: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK: $w0 = COPY [[C6]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @var1)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.if.then:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3
+ ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV4]](p0) :: (store (s32) into @var3)
+ ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1)
+ ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.if.end:
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C6]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, i32* @var1, align 4
%cmp = icmp eq i32 %0, 1
@@ -70,26 +75,31 @@ if.end:
define i32 @darwin_tls() {
; CHECK-LABEL: name: darwin_tls
; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; CHECK: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @tls_gv
- ; CHECK: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
- ; CHECK: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
- ; CHECK: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
- ; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.3
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2.if.then:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[LOAD1:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
- ; CHECK: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
- ; CHECK: G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2)
- ; CHECK: bb.3.if.end:
- ; CHECK: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
- ; CHECK: $w0 = COPY [[C2]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @tls_gv
+ ; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.3
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.if.then:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
+ ; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2
+ ; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2)
+ ; CHECK-NEXT: G_BR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.if.end:
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, i32* @var1, align 4
%cmp = icmp eq i32 %0, 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
index 154f00b96de35..aac252da8f3bf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
@@ -16,12 +16,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: tbnzx_and
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: TBNZX [[COPY]], 33, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: TBNZX [[COPY]], 33, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -46,13 +48,15 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: tbzx_and
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: TBZX [[COPY]], 33, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: TBZX [[COPY]], 33, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -77,13 +81,15 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: tbnzw_and
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: TBNZW [[COPY]], 0, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW [[COPY]], 0, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
@@ -108,13 +114,15 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: tbzw_and
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: TBZW [[COPY]], 0, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
@@ -139,14 +147,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: dont_fold_and_lt
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
@@ -171,14 +181,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: dont_fold_and_gt
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
- ; CHECK: Bcc 12, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
@@ -202,13 +214,15 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_and_not_power_of_2
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[COPY]], 4098
- ; CHECK: CBNZX [[ANDXri]], %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[COPY]], 4098
+ ; CHECK-NEXT: CBNZX [[ANDXri]], %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -232,14 +246,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_cmp_not_0
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8064
- ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv
- ; CHECK: Bcc 1, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8064
+ ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
index 1ef85e1a38d13..224b9dedd57d8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
@@ -13,13 +13,15 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fold_zext
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: TBNZW %copy, 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %copy, 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -44,13 +46,15 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fold_anyext
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: TBNZW %copy, 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %copy, 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -75,15 +79,17 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fold_multiple
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $h0
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub
- ; CHECK: %copy:gpr32all = COPY [[SUBREG_TO_REG]]
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy
- ; CHECK: TBNZW [[COPY]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $h0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub
+ ; CHECK-NEXT: %copy:gpr32all = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $h0
@@ -109,18 +115,20 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: dont_fold_more_than_one_use
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0
- ; CHECK: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %zext.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: $x0 = COPY %zext
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0
+ ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %zext.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: $x0 = COPY %zext
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
index d236a6c5ce59a..382999da00847 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
@@ -11,14 +11,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: fold_shl
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 2, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 2, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -46,15 +48,17 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_shl_1
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: %fold_me:gpr64 = UBFMXri %copy, 59, 58
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %fold_me.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: %fold_me:gpr64 = UBFMXri %copy, 59, 58
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %fold_me.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -82,16 +86,18 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_shl_2
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: %fold_cst:gpr64 = MOVi64imm -5
- ; CHECK: %fold_me:gpr64 = LSLVXr %copy, %fold_cst
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %fold_me.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: %fold_cst:gpr64 = MOVi64imm -5
+ ; CHECK-NEXT: %fold_me:gpr64 = LSLVXr %copy, %fold_cst
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %fold_me.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -120,17 +126,19 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_shl_3
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: %shl:gpr64 = UBFMXri %copy, 62, 61
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %shl.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: %second_use:gpr64sp = ORRXri %shl, 8000
- ; CHECK: $x0 = COPY %second_use
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: %shl:gpr64 = UBFMXri %copy, 62, 61
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %shl.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: %second_use:gpr64sp = ORRXri %shl, 8000
+ ; CHECK-NEXT: $x0 = COPY %second_use
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -161,14 +169,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: fold_ashr_in_range
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 4, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 4, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -198,12 +208,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: fold_ashr_msb_1
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: TBNZW %copy, 31, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %copy, 31, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -232,12 +244,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: fold_ashr_msb_2
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: TBNZX %copy, 63, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: TBNZX %copy, 63, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -266,12 +280,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: fold_lshr
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: TBNZW %copy, 4, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %copy, 4, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -300,12 +316,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: fold_lshr_2
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: TBNZX %copy, 32, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: TBNZX %copy, 32, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -335,14 +353,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_lshr
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: %fold_cst:gpr32 = MOVi32imm 29
- ; CHECK: %fold_me:gpr32 = LSRVWr %copy, %fold_cst
- ; CHECK: TBNZW %fold_me, 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: %fold_cst:gpr32 = MOVi32imm 29
+ ; CHECK-NEXT: %fold_me:gpr32 = LSRVWr %copy, %fold_cst
+ ; CHECK-NEXT: TBNZW %fold_me, 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -372,12 +392,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: lshr_negative
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: TBNZW %copy, 2, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %copy, 2, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
index 53ea6830fdc89..189d5e1f76041 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
@@ -9,14 +9,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: flip_eq
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -49,14 +51,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: flip_ne
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -84,14 +88,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_flip_eq
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -125,14 +131,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: dont_flip_eq_zext
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
- ; CHECK: TBNZX [[COPY1]], 63, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: TBNZX [[COPY1]], 63, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0(0x40000000), %bb.1(0x40000000)
@@ -156,14 +164,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_flip_ne
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -191,14 +201,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: xor_chain
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBZW [[COPY1]], 3, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
index 3d1d3af7221f0..0dd72599555c6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
@@ -20,18 +20,20 @@ body: |
; LOWER-LABEL: name: slt_to_sle_s32
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: slt_to_sle_s32
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32sp = COPY $w0
- ; SELECT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32sp = COPY $w0
+ ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 4097
%cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), %cst
@@ -54,18 +56,20 @@ body: |
; LOWER-LABEL: name: slt_to_sle_s64
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: slt_to_sle_s64
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64sp = COPY $x0
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64sp = COPY $x0
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 4097
%cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), %cst
@@ -88,18 +92,20 @@ body: |
; LOWER-LABEL: name: sge_to_sgt_s32
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s32), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: sge_to_sgt_s32
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32sp = COPY $w0
- ; SELECT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32sp = COPY $w0
+ ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 4097
%cmp:_(s32) = G_ICMP intpred(sge), %reg(s32), %cst
@@ -122,18 +128,20 @@ body: |
; LOWER-LABEL: name: sge_to_sgt_s64
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s64), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %reg(s64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: sge_to_sgt_s64
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64sp = COPY $x0
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64sp = COPY $x0
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 4097
%cmp:_(s32) = G_ICMP intpred(sge), %reg(s64), %cst
@@ -156,18 +164,20 @@ body: |
; LOWER-LABEL: name: ult_to_ule_s32
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(ule), %reg(s32), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ule), %reg(s32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: ult_to_ule_s32
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32sp = COPY $w0
- ; SELECT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32sp = COPY $w0
+ ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 4097
%cmp:_(s32) = G_ICMP intpred(ult), %reg(s32), %cst
@@ -190,18 +200,20 @@ body: |
; LOWER-LABEL: name: ult_to_ule_s64
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(ule), %reg(s64), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ule), %reg(s64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: ult_to_ule_s64
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64sp = COPY $x0
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64sp = COPY $x0
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 4097
%cmp:_(s32) = G_ICMP intpred(ult), %reg(s64), %cst
@@ -224,18 +236,20 @@ body: |
; LOWER-LABEL: name: uge_to_ugt_s32
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(ugt), %reg(s32), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ugt), %reg(s32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: uge_to_ugt_s32
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32sp = COPY $w0
- ; SELECT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32sp = COPY $w0
+ ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 4097
%cmp:_(s32) = G_ICMP intpred(uge), %reg(s32), %cst
@@ -258,18 +272,20 @@ body: |
; LOWER-LABEL: name: uge_to_ugt_s64
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(ugt), %reg(s64), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ugt), %reg(s64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: uge_to_ugt_s64
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64sp = COPY $x0
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64sp = COPY $x0
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 1, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 4097
%cmp:_(s32) = G_ICMP intpred(uge), %reg(s64), %cst
@@ -294,18 +310,20 @@ body: |
; LOWER-LABEL: name: sle_to_slt_s32
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8192
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8192
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: sle_to_slt_s32
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32sp = COPY $w0
- ; SELECT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 2, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32sp = COPY $w0
+ ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 2, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 8191
%cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), %cst
@@ -328,18 +346,20 @@ body: |
; LOWER-LABEL: name: sle_to_slt_s64
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8192
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8192
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: sle_to_slt_s64
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64sp = COPY $x0
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 2, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64sp = COPY $x0
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 2, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 8191
%cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), %cst
@@ -362,18 +382,20 @@ body: |
; LOWER-LABEL: name: sgt_to_sge_s32
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8192
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sge), %reg(s32), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8192
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %reg(s32), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: sgt_to_sge_s32
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32sp = COPY $w0
- ; SELECT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 2, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32sp = COPY $w0
+ ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 2, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 8191
%cmp:_(s32) = G_ICMP intpred(sgt), %reg(s32), %cst
@@ -396,18 +418,20 @@ body: |
; LOWER-LABEL: name: sgt_to_sge_s64
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8192
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sge), %reg(s64), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8192
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %reg(s64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: sgt_to_sge_s64
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64sp = COPY $x0
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 2, 12, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64sp = COPY $x0
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 2, 12, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 8191
%cmp:_(s32) = G_ICMP intpred(sgt), %reg(s64), %cst
@@ -433,19 +457,21 @@ body: |
; LOWER-LABEL: name: no_opt_int32_min
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: %cst:_(s32) = G_CONSTANT i32 -2147483648
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), %cst
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 -2147483648
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: no_opt_int32_min
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32 = COPY $w0
- ; SELECT: %cst:gpr32 = MOVi32imm -2147483648
- ; SELECT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg, %cst, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32 = COPY $w0
+ ; SELECT-NEXT: %cst:gpr32 = MOVi32imm -2147483648
+ ; SELECT-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg, %cst, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 -2147483648
%cmp:_(s32) = G_ICMP intpred(slt), %reg(s32), %cst
@@ -471,19 +497,21 @@ body: |
; LOWER-LABEL: name: no_opt_int64_min
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 -9223372036854775808
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), %cst
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 -9223372036854775808
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: no_opt_int64_min
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64 = COPY $x0
- ; SELECT: %cst:gpr64 = MOVi64imm -9223372036854775808
- ; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %reg, %cst, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64 = COPY $x0
+ ; SELECT-NEXT: %cst:gpr64 = MOVi64imm -9223372036854775808
+ ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %reg, %cst, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 -9223372036854775808
%cmp:_(s32) = G_ICMP intpred(slt), %reg(s64), %cst
@@ -509,19 +537,21 @@ body: |
; LOWER-LABEL: name: no_opt_int32_max
; LOWER: liveins: $w0
- ; LOWER: %reg:_(s32) = COPY $w0
- ; LOWER: %cst:_(s32) = G_CONSTANT i32 2147483647
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), %cst
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s32) = COPY $w0
+ ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 2147483647
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: no_opt_int32_max
; SELECT: liveins: $w0
- ; SELECT: %reg:gpr32 = COPY $w0
- ; SELECT: %cst:gpr32 = MOVi32imm 2147483647
- ; SELECT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg, %cst, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr32 = COPY $w0
+ ; SELECT-NEXT: %cst:gpr32 = MOVi32imm 2147483647
+ ; SELECT-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg, %cst, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 2147483647
%cmp:_(s32) = G_ICMP intpred(sle), %reg(s32), %cst
@@ -548,19 +578,21 @@ body: |
; LOWER-LABEL: name: no_opt_int64_max
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 9223372036854775807
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), %cst
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 9223372036854775807
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: no_opt_int64_max
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64 = COPY $x0
- ; SELECT: %cst:gpr64 = MOVi64imm 9223372036854775807
- ; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %reg, %cst, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64 = COPY $x0
+ ; SELECT-NEXT: %cst:gpr64 = MOVi64imm 9223372036854775807
+ ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %reg, %cst, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 9223372036854775807
%cmp:_(s32) = G_ICMP intpred(sle), %reg(s64), %cst
@@ -586,18 +618,20 @@ body: |
; LOWER-LABEL: name: no_opt_zero
; LOWER: liveins: $x0
- ; LOWER: %reg:_(s64) = COPY $x0
- ; LOWER: %cst:_(s64) = G_CONSTANT i64 0
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(ult), %reg(s64), %cst
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg:_(s64) = COPY $x0
+ ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ult), %reg(s64), %cst
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: no_opt_zero
; SELECT: liveins: $x0
- ; SELECT: %reg:gpr64sp = COPY $x0
- ; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 0, 0, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg:gpr64sp = COPY $x0
+ ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %reg, 0, 0, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 0
%cmp:_(s32) = G_ICMP intpred(ult), %reg(s64), %cst
@@ -618,22 +652,24 @@ body: |
; LOWER-LABEL: name: cmp_and_select
; LOWER: liveins: $w0, $w1
- ; LOWER: %reg0:_(s32) = COPY $w0
- ; LOWER: %reg1:_(s32) = COPY $w1
- ; LOWER: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %reg0(s32), [[C]]
- ; LOWER: %trunc:_(s1) = G_TRUNC %cmp(s32)
- ; LOWER: %select:_(s32) = G_SELECT %trunc(s1), %reg0, %reg1
- ; LOWER: $w0 = COPY %select(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg0:_(s32) = COPY $w0
+ ; LOWER-NEXT: %reg1:_(s32) = COPY $w1
+ ; LOWER-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %reg0(s32), [[C]]
+ ; LOWER-NEXT: %trunc:_(s1) = G_TRUNC %cmp(s32)
+ ; LOWER-NEXT: %select:_(s32) = G_SELECT %trunc(s1), %reg0, %reg1
+ ; LOWER-NEXT: $w0 = COPY %select(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: cmp_and_select
; SELECT: liveins: $w0, $w1
- ; SELECT: %reg0:gpr32common = COPY $w0
- ; SELECT: %reg1:gpr32 = COPY $w1
- ; SELECT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg0, 0, 0, implicit-def $nzcv
- ; SELECT: %select:gpr32 = CSELWr %reg0, %reg1, 11, implicit $nzcv
- ; SELECT: $w0 = COPY %select
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg0:gpr32common = COPY $w0
+ ; SELECT-NEXT: %reg1:gpr32 = COPY $w1
+ ; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg0, 0, 0, implicit-def $nzcv
+ ; SELECT-NEXT: %select:gpr32 = CSELWr %reg0, %reg1, 11, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %select
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:_(s32) = COPY $w0
%reg1:_(s32) = COPY $w1
%cst:_(s32) = G_CONSTANT i32 -1
@@ -656,20 +692,22 @@ body: |
; LOWER-LABEL: name: andsxri
; LOWER: liveins: $x0
- ; LOWER: %reg0:gpr(s64) = COPY $x0
- ; LOWER: %bit:gpr(s64) = G_CONSTANT i64 8
- ; LOWER: %and:gpr(s64) = G_AND %reg0, %bit
- ; LOWER: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
- ; LOWER: %cmp:gpr(s32) = G_ICMP intpred(sge), %and(s64), [[C]]
- ; LOWER: $w0 = COPY %cmp(s32)
- ; LOWER: RET_ReallyLR implicit $w0
+ ; LOWER-NEXT: {{ $}}
+ ; LOWER-NEXT: %reg0:gpr(s64) = COPY $x0
+ ; LOWER-NEXT: %bit:gpr(s64) = G_CONSTANT i64 8
+ ; LOWER-NEXT: %and:gpr(s64) = G_AND %reg0, %bit
+ ; LOWER-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0
+ ; LOWER-NEXT: %cmp:gpr(s32) = G_ICMP intpred(sge), %and(s64), [[C]]
+ ; LOWER-NEXT: $w0 = COPY %cmp(s32)
+ ; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: andsxri
; SELECT: liveins: $x0
- ; SELECT: %reg0:gpr64 = COPY $x0
- ; SELECT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %reg0, 8000, implicit-def $nzcv
- ; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
- ; SELECT: $w0 = COPY %cmp
- ; SELECT: RET_ReallyLR implicit $w0
+ ; SELECT-NEXT: {{ $}}
+ ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
+ ; SELECT-NEXT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %reg0, 8000, implicit-def $nzcv
+ ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
+ ; SELECT-NEXT: $w0 = COPY %cmp
+ ; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8
%and:gpr(s64) = G_AND %reg0, %bit
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
index 00fefddff1af1..e7fef25465aff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
@@ -13,12 +13,13 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_anyext_1
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_LOAD %0 :: (load (s8))
@@ -35,10 +36,11 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_anyext_s16
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 255
%2:_(s16) = G_LOAD %0 :: (load (s8))
@@ -55,9 +57,10 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_anyext_s32
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_LOAD %0 :: (load (s8))
@@ -73,9 +76,10 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_load_s32
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8), align 4)
- ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8), align 4)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_LOAD %0 :: (load (s32))
@@ -83,6 +87,26 @@ body: |
$w0 = COPY %3
...
+---
+name: test_load_s32_atomic
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_load_s32_atomic
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load seq_cst (s32))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s32) = G_CONSTANT i32 255
+ %2:_(s32) = G_LOAD %0 :: (load seq_cst (s32))
+ %3:_(s32) = G_AND %2, %1
+ $w0 = COPY %3
+...
---
name: test_load_mask_size_equals_dst_size
@@ -96,11 +120,12 @@ body: |
; CHECK-LABEL: name: test_load_mask_size_equals_dst_size
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
- ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 4294967295
%2:_(s32) = G_LOAD %0 :: (load (s32))
@@ -116,9 +141,10 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_zext
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8), align 2)
- ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8), align 2)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_ZEXTLOAD %0 :: (load (s16))
@@ -138,11 +164,12 @@ body: |
; CHECK-LABEL: name: test_zext_mask_larger_memsize
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ZEXTLOAD]], [[C]]
- ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ZEXTLOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 65535
%2:_(s32) = G_ZEXTLOAD %0 :: (load (s8))
@@ -158,9 +185,10 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_sext
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8), align 2)
- ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8), align 2)
+ ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_SEXTLOAD %0 :: (load (s16))
@@ -176,11 +204,12 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_sext_mask_larger_memsize
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C]]
- ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 65535
%2:_(s32) = G_SEXTLOAD %0 :: (load (s8))
@@ -196,12 +225,13 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_non_pow2_memtype
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s24) = G_CONSTANT i24 7
- ; CHECK: [[LOAD:%[0-9]+]]:_(s24) = G_LOAD [[COPY]](p0) :: (load (s24), align 4)
- ; CHECK: [[AND:%[0-9]+]]:_(s24) = G_AND [[LOAD]], [[C]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s24)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s24) = G_CONSTANT i24 7
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s24) = G_LOAD [[COPY]](p0) :: (load (s24), align 4)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s24) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s24)
+ ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
%0:_(p0) = COPY $x0
%1:_(s24) = G_CONSTANT i24 7
%2:_(s24) = G_LOAD %0 :: (load (s24))
@@ -219,11 +249,12 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_no_mask
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 510
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
- ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 510
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 510
%2:_(s32) = G_LOAD %0 :: (load (s8))
@@ -239,11 +270,12 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_volatile
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile load (s8))
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
- ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile load (s8))
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_LOAD %0 :: (volatile load (s8))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
index fff083a17dada..3745c2119b524 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
@@ -13,24 +13,29 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test_loop_phi_fpr_to_gpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
- ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
- ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
- ; CHECK: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
- ; CHECK: B %bb.2
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
+ ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
+ ; CHECK-NEXT: B %bb.2
bb.0:
successors: %bb.1(0x80000000)
@@ -67,24 +72,29 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test_loop_phi_gpr_to_fpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
- ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
- ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
- ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
- ; CHECK: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
- ; CHECK: B %bb.2
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
+ ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+ ; CHECK-NEXT: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
+ ; CHECK-NEXT: B %bb.2
bb.0:
successors: %bb.1(0x80000000)
@@ -115,50 +125,60 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
+ ; CHECK-LABEL: name: multiple_phis
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000)
+ ; CHECK-NEXT: liveins: $w0, $w1, $x2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:gpr64sp = COPY $x2
+ ; CHECK-NEXT: %cond_1:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: %gpr_1:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %gpr_1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
+ ; CHECK-NEXT: TBNZW %cond_1, 0, %bb.5
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond_2:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: TBNZW %cond_2, 0, %bb.3
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %gpr_2:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: B %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %fpr:fpr16 = IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.5(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %fp_phi:fpr16 = PHI %fpr, %bb.3, [[COPY1]], %bb.2
+ ; CHECK-NEXT: %gp_phi1:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
+ ; CHECK-NEXT: %gp_phi2:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
+ ; CHECK-NEXT: %gp_phi3:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %fp_phi, %subreg.hsub
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: %use_fp_phi:gpr32 = PHI %gpr_1, %bb.0, [[COPY2]], %bb.4
+ ; CHECK-NEXT: %use_gp_phi1:gpr32 = PHI %gpr_1, %bb.0, %gp_phi1, %bb.4
+ ; CHECK-NEXT: %use_gp_phi2:gpr32 = PHI %gpr_1, %bb.0, %gp_phi2, %bb.4
+ ; CHECK-NEXT: %use_gp_phi3:gpr32 = PHI %gpr_1, %bb.0, %gp_phi3, %bb.4
+ ; CHECK-NEXT: STRHHui %use_fp_phi, %ptr, 0 :: (store (s16))
+ ; CHECK-NEXT: STRHHui %use_gp_phi1, %ptr, 0 :: (store (s16))
+ ; CHECK-NEXT: STRHHui %use_gp_phi2, %ptr, 0 :: (store (s16))
+ ; CHECK-NEXT: STRHHui %use_gp_phi3, %ptr, 0 :: (store (s16))
+ ; CHECK-NEXT: RET_ReallyLR
; The copy we insert in bb.4 should appear after all the phi instructions.
- ; CHECK-LABEL: name: multiple_phis
- ; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.5(0x40000000)
- ; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %ptr:gpr64sp = COPY $x2
- ; CHECK: %cond_1:gpr32 = IMPLICIT_DEF
- ; CHECK: %gpr_1:gpr32 = IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %gpr_1
- ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
- ; CHECK: TBNZW %cond_1, 0, %bb.5
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; CHECK: %cond_2:gpr32 = IMPLICIT_DEF
- ; CHECK: TBNZW %cond_2, 0, %bb.3
- ; CHECK: B %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: %gpr_2:gpr32 = IMPLICIT_DEF
- ; CHECK: B %bb.4
- ; CHECK: bb.3:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: %fpr:fpr16 = IMPLICIT_DEF
- ; CHECK: bb.4:
- ; CHECK: successors: %bb.5(0x80000000)
- ; CHECK: %fp_phi:fpr16 = PHI %fpr, %bb.3, [[COPY1]], %bb.2
- ; CHECK: %gp_phi1:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
- ; CHECK: %gp_phi2:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
- ; CHECK: %gp_phi3:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %fp_phi, %subreg.hsub
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
- ; CHECK: bb.5:
- ; CHECK: %use_fp_phi:gpr32 = PHI %gpr_1, %bb.0, [[COPY2]], %bb.4
- ; CHECK: %use_gp_phi1:gpr32 = PHI %gpr_1, %bb.0, %gp_phi1, %bb.4
- ; CHECK: %use_gp_phi2:gpr32 = PHI %gpr_1, %bb.0, %gp_phi2, %bb.4
- ; CHECK: %use_gp_phi3:gpr32 = PHI %gpr_1, %bb.0, %gp_phi3, %bb.4
- ; CHECK: STRHHui %use_fp_phi, %ptr, 0 :: (store (s16))
- ; CHECK: STRHHui %use_gp_phi1, %ptr, 0 :: (store (s16))
- ; CHECK: STRHHui %use_gp_phi2, %ptr, 0 :: (store (s16))
- ; CHECK: STRHHui %use_gp_phi3, %ptr, 0 :: (store (s16))
- ; CHECK: RET_ReallyLR
bb.1:
successors: %bb.2, %bb.6
liveins: $w0, $w1, $x2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
index c7d01ff5a460e..b35f45a7bb56f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
@@ -18,10 +18,11 @@ body: |
; CHECK-LABEL: name: gpr
; CHECK: liveins: $w0, $w1
- ; CHECK: %copy:gpr(s32) = COPY $w0
- ; CHECK: %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
- ; CHECK: $w1 = COPY %copy_assert_sext(s32)
- ; CHECK: RET_ReallyLR implicit $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: $w1 = COPY %copy_assert_sext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w1
%copy:_(s32) = COPY $w0
%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
$w1 = COPY %copy_assert_sext(s32)
@@ -41,10 +42,11 @@ body: |
; CHECK-LABEL: name: gpr_vector
; CHECK: liveins: $x0, $x1
- ; CHECK: %copy:gpr(<2 x s32>) = COPY $x0
- ; CHECK: %copy_assert_sext:gpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
- ; CHECK: $x1 = COPY %copy_assert_sext(<2 x s32>)
- ; CHECK: RET_ReallyLR implicit $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr(<2 x s32>) = COPY $x0
+ ; CHECK-NEXT: %copy_assert_sext:gpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: $x1 = COPY %copy_assert_sext(<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x1
%copy:_(<2 x s32>) = COPY $x0
%copy_assert_sext:_(<2 x s32>) = G_ASSERT_SEXT %copy(<2 x s32>), 16
$x1 = COPY %copy_assert_sext(<2 x s32>)
@@ -64,10 +66,11 @@ body: |
; CHECK-LABEL: name: fpr
; CHECK: liveins: $s0, $s1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
- ; CHECK: $s1 = COPY %copy_assert_sext(s32)
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: $s1 = COPY %copy_assert_sext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
%copy:_(s32) = COPY $s0
%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
$s1 = COPY %copy_assert_sext(s32)
@@ -87,10 +90,11 @@ body: |
; CHECK-LABEL: name: fpr_vector
; CHECK: liveins: $d0, $d1
- ; CHECK: %copy:fpr(<2 x s32>) = COPY $d0
- ; CHECK: %copy_assert_sext:fpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
- ; CHECK: $d1 = COPY %copy_assert_sext(<2 x s32>)
- ; CHECK: RET_ReallyLR implicit $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: %copy_assert_sext:fpr(<2 x s32>) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: $d1 = COPY %copy_assert_sext(<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d1
%copy:_(<2 x s32>) = COPY $d0
%copy_assert_sext:_(<2 x s32>) = G_ASSERT_SEXT %copy(<2 x s32>), 16
$d1 = COPY %copy_assert_sext(<2 x s32>)
@@ -108,10 +112,11 @@ body: |
; CHECK-LABEL: name: in_between_cross_bank_copy
; CHECK: liveins: $s0, $w1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
- ; CHECK: $w1 = COPY %copy_assert_sext(s32)
- ; CHECK: RET_ReallyLR implicit $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: $w1 = COPY %copy_assert_sext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w1
%copy:_(s32) = COPY $s0
%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
$w1 = COPY %copy_assert_sext(s32)
@@ -132,11 +137,12 @@ body: |
; CHECK-LABEL: name: fpr_feeding_store
; CHECK: liveins: $x0, $s0, $s1
- ; CHECK: %ptr:gpr(p0) = COPY $x0
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
- ; CHECK: G_STORE %copy_assert_sext(s32), %ptr(p0) :: (store (s32))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: G_STORE %copy_assert_sext(s32), %ptr(p0) :: (store (s32))
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%copy:_(s32) = COPY $s0
%copy_assert_sext:_(s32) = G_ASSERT_SEXT %copy(s32), 16
@@ -158,15 +164,16 @@ body: |
; CHECK-LABEL: name: fpr_feeding_select
; CHECK: liveins: $d0, $x1, $w0
- ; CHECK: %w0:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %w0(s32)
- ; CHECK: %fpr:fpr(s64) = COPY $d0
- ; CHECK: %fpr_assert_sext:fpr(s64) = G_ASSERT_SEXT %fpr, 32
- ; CHECK: %gpr:gpr(s64) = COPY $x1
- ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
- ; CHECK: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_sext, [[COPY]]
- ; CHECK: $d0 = COPY %select(s64)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %w0:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %w0(s32)
+ ; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
+ ; CHECK-NEXT: %fpr_assert_sext:fpr(s64) = G_ASSERT_SEXT %fpr, 32
+ ; CHECK-NEXT: %gpr:gpr(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
+ ; CHECK-NEXT: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_sext, [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY %select(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%w0:_(s32) = COPY $w0
%cond:_(s1) = G_TRUNC %w0(s32)
%fpr:_(s64) = COPY $d0
@@ -185,24 +192,29 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fpr_feeding_phi
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $s0, $w1
- ; CHECK: %copy1:fpr(s32) = COPY $s0
- ; CHECK: %copy2:gpr(s32) = COPY $w1
- ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy1, 16
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
- ; CHECK: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
- ; CHECK: G_BRCOND %cmp_trunc(s1), %bb.1
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %bb1_val:gpr(s32) = COPY %copy2(s32)
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.0(0x80000000)
- ; CHECK: %phi:fpr(s32) = G_PHI %copy_assert_sext(s32), %bb.0, %bb1_val(s32), %bb.1
- ; CHECK: G_BR %bb.0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $s0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy2:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy1, 16
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
+ ; CHECK-NEXT: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
+ ; CHECK-NEXT: G_BRCOND %cmp_trunc(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.0(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %phi:fpr(s32) = G_PHI %copy_assert_sext(s32), %bb.0, %bb1_val(s32), %bb.1
+ ; CHECK-NEXT: G_BR %bb.0
bb.0:
successors: %bb.1, %bb.2
liveins: $s0, $w1
@@ -235,25 +247,30 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fed_by_fpr_phi
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $s0, $s1
- ; CHECK: %copy1:fpr(s32) = COPY $s0
- ; CHECK: %copy2:fpr(s32) = COPY $s1
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
- ; CHECK: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
- ; CHECK: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
- ; CHECK: G_BRCOND %cmp_trunc(s1), %bb.1
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %bb1_val:gpr(s32) = COPY %copy2(s32)
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.0(0x80000000)
- ; CHECK: %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
- ; CHECK: %assert_sext:fpr(s32) = G_ASSERT_SEXT %phi, 16
- ; CHECK: G_BR %bb.0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy2:fpr(s32) = COPY $s1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
+ ; CHECK-NEXT: G_BRCOND %cmp_trunc(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.0(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
+ ; CHECK-NEXT: %assert_sext:fpr(s32) = G_ASSERT_SEXT %phi, 16
+ ; CHECK-NEXT: G_BR %bb.0
bb.0:
successors: %bb.1, %bb.2
liveins: $s0, $s1
@@ -283,14 +300,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name:
diff erent_blocks_gpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $w0, $w1
- ; CHECK: %copy:gpr(s32) = COPY $w0
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
- ; CHECK: $w1 = COPY %copy_assert_sext(s32)
- ; CHECK: RET_ReallyLR implicit $w1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: $w1 = COPY %copy_assert_sext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w1
bb.0:
successors: %bb.1
liveins: $w0, $w1
@@ -311,14 +330,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name:
diff erent_blocks_fpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $s0, $s1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
- ; CHECK: $s1 = COPY %copy_assert_sext(s32)
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: $s1 = COPY %copy_assert_sext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1
liveins: $s0, $s1
@@ -340,19 +361,24 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name:
diff erent_blocks_fpr_backedge
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $s0, $s1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %copy_assert_sext1:fpr(s32) = G_ASSERT_SEXT %copy, 16
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.0(0x80000000)
- ; CHECK: %copy_assert_sext2:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext1, 16
- ; CHECK: %copy_assert_sext3:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext2, 16
- ; CHECK: G_BR %bb.0
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy_assert_sext1:fpr(s32) = G_ASSERT_SEXT %copy, 16
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.0(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy_assert_sext2:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext1, 16
+ ; CHECK-NEXT: %copy_assert_sext3:fpr(s32) = G_ASSERT_SEXT %copy_assert_sext2, 16
+ ; CHECK-NEXT: G_BR %bb.0
bb.0:
successors: %bb.1
liveins: $s0, $s1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
index 592bd1f8d4a9f..a26a9b1f9eb5e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
@@ -18,10 +18,11 @@ body: |
; CHECK-LABEL: name: gpr
; CHECK: liveins: $w0, $w1
- ; CHECK: %copy:gpr(s32) = COPY $w0
- ; CHECK: %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: $w1 = COPY %copy_assert_zext(s32)
- ; CHECK: RET_ReallyLR implicit $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: $w1 = COPY %copy_assert_zext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w1
%copy:_(s32) = COPY $w0
%copy_assert_zext:_(s32) = G_ASSERT_ZEXT %copy(s32), 16
$w1 = COPY %copy_assert_zext(s32)
@@ -41,10 +42,11 @@ body: |
; CHECK-LABEL: name: gpr_vector
; CHECK: liveins: $x0, $x1
- ; CHECK: %copy:gpr(<2 x s32>) = COPY $x0
- ; CHECK: %copy_assert_zext:gpr(<2 x s32>) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: $x1 = COPY %copy_assert_zext(<2 x s32>)
- ; CHECK: RET_ReallyLR implicit $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr(<2 x s32>) = COPY $x0
+ ; CHECK-NEXT: %copy_assert_zext:gpr(<2 x s32>) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: $x1 = COPY %copy_assert_zext(<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x1
%copy:_(<2 x s32>) = COPY $x0
%copy_assert_zext:_(<2 x s32>) = G_ASSERT_ZEXT %copy(<2 x s32>), 16
$x1 = COPY %copy_assert_zext(<2 x s32>)
@@ -64,10 +66,11 @@ body: |
; CHECK-LABEL: name: fpr
; CHECK: liveins: $s0, $s1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: $s1 = COPY %copy_assert_zext(s32)
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: $s1 = COPY %copy_assert_zext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
%copy:_(s32) = COPY $s0
%copy_assert_zext:_(s32) = G_ASSERT_ZEXT %copy(s32), 16
$s1 = COPY %copy_assert_zext(s32)
@@ -87,10 +90,11 @@ body: |
; CHECK-LABEL: name: fpr_vector
; CHECK: liveins: $d0, $d1
- ; CHECK: %copy:fpr(<2 x s32>) = COPY $d0
- ; CHECK: %copy_assert_zext:fpr(<2 x s32>) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: $d1 = COPY %copy_assert_zext(<2 x s32>)
- ; CHECK: RET_ReallyLR implicit $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: %copy_assert_zext:fpr(<2 x s32>) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: $d1 = COPY %copy_assert_zext(<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d1
%copy:_(<2 x s32>) = COPY $d0
%copy_assert_zext:_(<2 x s32>) = G_ASSERT_ZEXT %copy(<2 x s32>), 16
$d1 = COPY %copy_assert_zext(<2 x s32>)
@@ -108,10 +112,11 @@ body: |
; CHECK-LABEL: name: in_between_cross_bank_copy
; CHECK: liveins: $s0, $w1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: $w1 = COPY %copy_assert_zext(s32)
- ; CHECK: RET_ReallyLR implicit $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: $w1 = COPY %copy_assert_zext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w1
%copy:_(s32) = COPY $s0
%copy_assert_zext:_(s32) = G_ASSERT_ZEXT %copy(s32), 16
$w1 = COPY %copy_assert_zext(s32)
@@ -132,11 +137,12 @@ body: |
; CHECK-LABEL: name: fpr_feeding_store
; CHECK: liveins: $x0, $s0, $s1
- ; CHECK: %ptr:gpr(p0) = COPY $x0
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: G_STORE %copy_assert_zext(s32), %ptr(p0) :: (store (s32))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: G_STORE %copy_assert_zext(s32), %ptr(p0) :: (store (s32))
+ ; CHECK-NEXT: RET_ReallyLR
%ptr:_(p0) = COPY $x0
%copy:_(s32) = COPY $s0
%copy_assert_zext:_(s32) = G_ASSERT_ZEXT %copy(s32), 16
@@ -158,15 +164,16 @@ body: |
; CHECK-LABEL: name: fpr_feeding_select
; CHECK: liveins: $d0, $x1, $w0
- ; CHECK: %w0:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %w0(s32)
- ; CHECK: %fpr:fpr(s64) = COPY $d0
- ; CHECK: %fpr_assert_zext:fpr(s64) = G_ASSERT_ZEXT %fpr, 32
- ; CHECK: %gpr:gpr(s64) = COPY $x1
- ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
- ; CHECK: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_zext, [[COPY]]
- ; CHECK: $d0 = COPY %select(s64)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %w0:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %w0(s32)
+ ; CHECK-NEXT: %fpr:fpr(s64) = COPY $d0
+ ; CHECK-NEXT: %fpr_assert_zext:fpr(s64) = G_ASSERT_ZEXT %fpr, 32
+ ; CHECK-NEXT: %gpr:gpr(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
+ ; CHECK-NEXT: %select:fpr(s64) = G_SELECT %cond(s1), %fpr_assert_zext, [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY %select(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%w0:_(s32) = COPY $w0
%cond:_(s1) = G_TRUNC %w0(s32)
%fpr:_(s64) = COPY $d0
@@ -185,24 +192,29 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fpr_feeding_phi
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $s0, $w1
- ; CHECK: %copy1:fpr(s32) = COPY $s0
- ; CHECK: %copy2:gpr(s32) = COPY $w1
- ; CHECK: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy1, 16
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
- ; CHECK: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
- ; CHECK: G_BRCOND %cmp_trunc(s1), %bb.1
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %bb1_val:gpr(s32) = COPY %copy2(s32)
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.0(0x80000000)
- ; CHECK: %phi:fpr(s32) = G_PHI %copy_assert_zext(s32), %bb.0, %bb1_val(s32), %bb.1
- ; CHECK: G_BR %bb.0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $s0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy2:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy1, 16
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), %copy2
+ ; CHECK-NEXT: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
+ ; CHECK-NEXT: G_BRCOND %cmp_trunc(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.0(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %phi:fpr(s32) = G_PHI %copy_assert_zext(s32), %bb.0, %bb1_val(s32), %bb.1
+ ; CHECK-NEXT: G_BR %bb.0
bb.0:
successors: %bb.1, %bb.2
liveins: $s0, $w1
@@ -235,25 +247,30 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fed_by_fpr_phi
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $s0, $s1
- ; CHECK: %copy1:fpr(s32) = COPY $s0
- ; CHECK: %copy2:fpr(s32) = COPY $s1
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
- ; CHECK: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
- ; CHECK: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
- ; CHECK: G_BRCOND %cmp_trunc(s1), %bb.1
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %bb1_val:gpr(s32) = COPY %copy2(s32)
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.0(0x80000000)
- ; CHECK: %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
- ; CHECK: %assert_zext:fpr(s32) = G_ASSERT_ZEXT %phi, 16
- ; CHECK: G_BR %bb.0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %copy2:fpr(s32) = COPY $s1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %copy1(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
+ ; CHECK-NEXT: G_BRCOND %cmp_trunc(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %bb1_val:gpr(s32) = COPY %copy2(s32)
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.0(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %phi:fpr(s32) = G_PHI %copy1(s32), %bb.0, %bb1_val(s32), %bb.1
+ ; CHECK-NEXT: %assert_zext:fpr(s32) = G_ASSERT_ZEXT %phi, 16
+ ; CHECK-NEXT: G_BR %bb.0
bb.0:
successors: %bb.1, %bb.2
liveins: $s0, $s1
@@ -283,14 +300,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name:
diff erent_blocks_gpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $w0, $w1
- ; CHECK: %copy:gpr(s32) = COPY $w0
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: $w1 = COPY %copy_assert_zext(s32)
- ; CHECK: RET_ReallyLR implicit $w1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: $w1 = COPY %copy_assert_zext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w1
bb.0:
successors: %bb.1
liveins: $w0, $w1
@@ -311,14 +330,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name:
diff erent_blocks_fpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $s0, $s1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: $s1 = COPY %copy_assert_zext(s32)
- ; CHECK: RET_ReallyLR implicit $s1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: $s1 = COPY %copy_assert_zext(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1
liveins: $s0, $s1
@@ -340,19 +361,24 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name:
diff erent_blocks_fpr_backedge
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $s0, $s1
- ; CHECK: %copy:fpr(s32) = COPY $s0
- ; CHECK: G_BR %bb.1
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %copy_assert_zext1:fpr(s32) = G_ASSERT_ZEXT %copy, 16
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.0(0x80000000)
- ; CHECK: %copy_assert_zext2:fpr(s32) = G_ASSERT_ZEXT %copy_assert_zext1, 16
- ; CHECK: %copy_assert_zext3:fpr(s32) = G_ASSERT_ZEXT %copy_assert_zext2, 16
- ; CHECK: G_BR %bb.0
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $s0, $s1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: G_BR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy_assert_zext1:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.0(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy_assert_zext2:fpr(s32) = G_ASSERT_ZEXT %copy_assert_zext1, 16
+ ; CHECK-NEXT: %copy_assert_zext3:fpr(s32) = G_ASSERT_ZEXT %copy_assert_zext2, 16
+ ; CHECK-NEXT: G_BR %bb.0
bb.0:
successors: %bb.1
liveins: $s0, $s1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
index a9aa47af2a341..9f5a57b09301b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
@@ -22,12 +22,13 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_only_uses_fp
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
- ; CHECK: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[C]](s32), [[LOAD]]
- ; CHECK: $w0 = COPY [[FCMP]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[C]](s32), [[LOAD]]
+ ; CHECK-NEXT: $w0 = COPY [[FCMP]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(s32) = G_FCONSTANT float 2.0
%2:_(s32) = G_LOAD %0 :: (load (s32))
@@ -45,12 +46,13 @@ body: |
liveins: $x0
; CHECK-LABEL: name: unmerge_only_uses_fp
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY [[COPY]](s64)
- ; CHECK: [[UV:%[0-9]+]]:fpr(s32), [[UV1:%[0-9]+]]:fpr(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
- ; CHECK: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[UV]](s32), [[UV1]]
- ; CHECK: $w0 = COPY [[FCMP]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:fpr(s32), [[UV1:%[0-9]+]]:fpr(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
+ ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[UV]](s32), [[UV1]]
+ ; CHECK-NEXT: $w0 = COPY [[FCMP]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s64) = COPY $x0
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
%3:_(s32) = G_FCMP floatpred(uno), %1, %2
@@ -67,10 +69,11 @@ body: |
liveins: $x0, $w1
; CHECK-LABEL: name: store_defined_by_fp
; CHECK: liveins: $x0, $w1
- ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
- ; CHECK: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
- ; CHECK: G_STORE [[SITOFP]](s32), [[COPY]](p0) :: (store (s32))
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
+ ; CHECK-NEXT: G_STORE [[SITOFP]](s32), [[COPY]](p0) :: (store (s32))
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(s32) = G_SITOFP %1
@@ -86,14 +89,15 @@ body: |
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: select_defined_by_fp_using_fp
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC %2(s32)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
- ; CHECK: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
- ; CHECK: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[SITOFP]]
- ; CHECK: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[SELECT]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC %2(s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[SITOFP]]
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[SELECT]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %3(s32)
%2:_(s32) = COPY $w1
@@ -110,22 +114,26 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: load_used_by_phi_fpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
- ; CHECK: %cond_wide:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
- ; CHECK: %fpr_copy:fpr(s32) = COPY $s0
- ; CHECK: %ptr:gpr(p0) = COPY $x0
- ; CHECK: G_BRCOND %cond(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %load(s32), %bb.1
- ; CHECK: $s0 = COPY %phi(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x0, $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond_wide:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
+ ; CHECK-NEXT: %fpr_copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %ptr:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %load(s32), %bb.1
+ ; CHECK-NEXT: $s0 = COPY %phi(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $x0, $s0, $s1, $w0, $w1
@@ -152,22 +160,26 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: load_used_by_phi_gpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
- ; CHECK: %cond_wide:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
- ; CHECK: %gpr_copy:gpr(s32) = COPY $w1
- ; CHECK: %ptr:gpr(p0) = COPY $x0
- ; CHECK: G_BRCOND %cond(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %load(s32), %bb.1
- ; CHECK: $s0 = COPY %phi(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x0, $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond_wide:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
+ ; CHECK-NEXT: %gpr_copy:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: %ptr:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %load:gpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %load(s32), %bb.1
+ ; CHECK-NEXT: $s0 = COPY %phi(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $x0, $s0, $s1, $w0, $w1
@@ -194,23 +206,27 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: select_used_by_phi_fpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cond_wide:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
- ; CHECK: %fpr_copy:fpr(s32) = COPY $s0
- ; CHECK: %gpr_copy:gpr(s32) = COPY $w1
- ; CHECK: G_BRCOND %cond(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %gpr_copy(s32)
- ; CHECK: %select:fpr(s32) = G_SELECT %cond(s1), %fpr_copy, [[COPY]]
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %select(s32), %bb.1
- ; CHECK: $w0 = COPY %phi(s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond_wide:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
+ ; CHECK-NEXT: %fpr_copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %gpr_copy:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY %gpr_copy(s32)
+ ; CHECK-NEXT: %select:fpr(s32) = G_SELECT %cond(s1), %fpr_copy, [[COPY]]
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %select(s32), %bb.1
+ ; CHECK-NEXT: $w0 = COPY %phi(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
; The G_SELECT and G_PHI should end up with the same register bank.
;
bb.0:
@@ -239,23 +255,27 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: select_used_by_phi_gpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $s0, $s1, $w0, $w1
- ; CHECK: %cond_wide:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
- ; CHECK: %fpr_copy:fpr(s32) = COPY $s0
- ; CHECK: %gpr_copy:gpr(s32) = COPY $w1
- ; CHECK: G_BRCOND %cond(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %fpr_copy(s32)
- ; CHECK: %select:gpr(s32) = G_SELECT %cond(s1), [[COPY]], %gpr_copy
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %select(s32), %bb.1
- ; CHECK: $s0 = COPY %phi(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond_wide:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
+ ; CHECK-NEXT: %fpr_copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %gpr_copy:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %fpr_copy(s32)
+ ; CHECK-NEXT: %select:gpr(s32) = G_SELECT %cond(s1), [[COPY]], %gpr_copy
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %select(s32), %bb.1
+ ; CHECK-NEXT: $s0 = COPY %phi(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
; The G_SELECT and G_PHI should end up with the same register bank.
;
bb.0:
@@ -285,23 +305,27 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: unmerge_used_by_phi_fpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
- ; CHECK: %cond_wide:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
- ; CHECK: %fpr_copy:fpr(s32) = COPY $s0
- ; CHECK: %unmerge_src:gpr(s64) = COPY $x0
- ; CHECK: G_BRCOND %cond(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %unmerge_src(s64)
- ; CHECK: %unmerge_1:fpr(s32), %unmerge_2:fpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
- ; CHECK: $s0 = COPY %phi(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x0, $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond_wide:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
+ ; CHECK-NEXT: %fpr_copy:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: %unmerge_src:gpr(s64) = COPY $x0
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY %unmerge_src(s64)
+ ; CHECK-NEXT: %unmerge_1:fpr(s32), %unmerge_2:fpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
+ ; CHECK-NEXT: $s0 = COPY %phi(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $x0, $s0, $s1, $w0, $w1
@@ -328,22 +352,26 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: unmerge_used_by_phi_gpr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
- ; CHECK: %cond_wide:gpr(s32) = COPY $w0
- ; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
- ; CHECK: %gpr_copy:gpr(s32) = COPY $w1
- ; CHECK: %unmerge_src:gpr(s64) = COPY $x0
- ; CHECK: G_BRCOND %cond(s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: %unmerge_1:gpr(s32), %unmerge_2:gpr(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
- ; CHECK: $s0 = COPY %phi(s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x0, $s0, $s1, $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %cond_wide:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
+ ; CHECK-NEXT: %gpr_copy:gpr(s32) = COPY $w1
+ ; CHECK-NEXT: %unmerge_src:gpr(s64) = COPY $x0
+ ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %unmerge_1:gpr(s32), %unmerge_2:gpr(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
+ ; CHECK-NEXT: G_BR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
+ ; CHECK-NEXT: $s0 = COPY %phi(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $x0, $s0, $s1, $w0, $w1
@@ -374,11 +402,12 @@ body: |
; The sitofp should assign both src and dest to FPR, resulting in no copies.
; CHECK-LABEL: name: load_used_by_sitofp
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
- ; CHECK: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[LOAD]](s32)
- ; CHECK: $s0 = COPY [[SITOFP]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[LOAD]](s32)
+ ; CHECK-NEXT: $s0 = COPY [[SITOFP]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:_(p0) = COPY $x0
%1:_(s32) = G_LOAD %0 :: (load (s32))
%2:_(s32) = G_SITOFP %1:_(s32)
@@ -394,11 +423,12 @@ body: |
liveins: $x0
; CHECK-LABEL: name: load_used_by_uitofp
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
- ; CHECK: [[UITOFP:%[0-9]+]]:fpr(s32) = G_UITOFP [[LOAD]](s32)
- ; CHECK: $s0 = COPY [[UITOFP]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:fpr(s32) = G_UITOFP [[LOAD]](s32)
+ ; CHECK-NEXT: $s0 = COPY [[UITOFP]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:_(p0) = COPY $x0
%1:_(s32) = G_LOAD %0 :: (load (s32))
%2:_(s32) = G_UITOFP %1:_(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
index c0fa01e074d96..40ce8060fd825 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
@@ -14,13 +14,14 @@ body: |
; CHECK-LABEL: name: select_f32
; CHECK: liveins: $s0, $s1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s0
- ; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s1
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
- ; CHECK: $s0 = COPY [[SELECT]](s32)
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $s0 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%3:_(s32) = COPY $w0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s32) = COPY $s0
@@ -42,13 +43,14 @@ body: |
; CHECK-LABEL: name: select_f64
; CHECK: liveins: $d0, $d1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
- ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
- ; CHECK: $d0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%3:_(s32) = COPY $w0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s64) = COPY $d0
@@ -67,15 +69,6 @@ machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1, $w0
- ; CHECK-LABEL: name: two_fpr_inputs_gpr_output
- ; CHECK: liveins: $d0, $d1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
- ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
; Verify that the G_SELECT only has FPRs.
; The only
diff erence between fcsel and csel are the register banks. So,
@@ -83,6 +76,16 @@ body: |
; select anyway. This will cost one copy for the output, but that's less
; than doing two to put the inputs on GPRs.
+ ; CHECK-LABEL: name: two_fpr_inputs_gpr_output
+ ; CHECK: liveins: $d0, $d1, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%3:_(s32) = COPY $w0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s64) = COPY $d0
@@ -101,20 +104,21 @@ machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $x1, $w0
- ; CHECK-LABEL: name: one_fpr_input_fpr_output
- ; CHECK: liveins: $d0, $x1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
- ; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
- ; CHECK: [[COPY3:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY3]]
- ; CHECK: $d0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $d0
; Same idea as the above test. If the output is an FPR, and one of the
; inputs is an FPR, then it's fewer copies to just do a FCSEL.
+ ; CHECK-LABEL: name: one_fpr_input_fpr_output
+ ; CHECK: liveins: $d0, $x1, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY3]]
+ ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%3:_(s32) = COPY $w0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s64) = COPY $d0
@@ -133,20 +137,21 @@ machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $x1, $w0
- ; CHECK-LABEL: name: one_fpr_input_gpr_output
- ; CHECK: liveins: $d0, $x1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
- ; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
- ; CHECK: [[COPY3:%[0-9]+]]:gpr(s64) = COPY [[COPY1]](s64)
- ; CHECK: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[COPY2]]
- ; CHECK: $x0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $x0
; Now we have more GPR registers on the G_SELECT. It's cheaper here to put
; everything on GPR.
+ ; CHECK-LABEL: name: one_fpr_input_gpr_output
+ ; CHECK: liveins: $d0, $x1, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr(s64) = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[COPY2]]
+ ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%3:_(s32) = COPY $w0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s64) = COPY $d0
@@ -165,18 +170,19 @@ machineFunctionInfo: {}
body: |
bb.0:
liveins: $x0, $x1, $w0
- ; CHECK-LABEL: name: two_gpr_input_fpr_output
- ; CHECK: liveins: $x0, $x1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
- ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $x0
- ; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
- ; CHECK: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
- ; CHECK: $d0 = COPY [[SELECT]](s64)
- ; CHECK: RET_ReallyLR implicit $d0
; Same as above. The G_SELECT should get all GPRS.
+ ; CHECK-LABEL: name: two_gpr_input_fpr_output
+ ; CHECK: liveins: $x0, $x1, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $x0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%3:_(s32) = COPY $w0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
index d8e4a549148fd..8fb939b0708cd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
@@ -9,14 +9,17 @@ liveins:
body: |
; CHECK-LABEL: name: condbr_of_not
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
- ; CHECK: TBZW [[LDRBBui]], 0, %bb.2
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: TBZW [[LDRBBui]], 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
successors: %bb.2, %bb.3
liveins: $x0
@@ -45,14 +48,17 @@ liveins:
body: |
; CHECK-LABEL: name: condbr_of_not_64
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
- ; CHECK: TBZW [[LDRBBui]], 0, %bb.2
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: TBZW [[LDRBBui]], 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
; TB(N)ZX has no encoding if the bit being tested is < 32, so we should get
; TBZW here.
;
@@ -82,13 +88,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: condbr_of_and
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: %lhs:gpr32 = COPY $w0
- ; CHECK: TBNZW %lhs, 0, %bb.2
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %lhs:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %lhs, 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
successors: %bb.2, %bb.3
liveins: $w0
@@ -112,15 +121,18 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: condbr_of_and_no_cst
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: %lhs:gpr32 = COPY $w0
- ; CHECK: %rhs:gpr32 = COPY $w1
- ; CHECK: %op:gpr32 = ANDWrr %lhs, %rhs
- ; CHECK: TBNZW %op, 0, %bb.2
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %lhs:gpr32 = COPY $w0
+ ; CHECK-NEXT: %rhs:gpr32 = COPY $w1
+ ; CHECK-NEXT: %op:gpr32 = ANDWrr %lhs, %rhs
+ ; CHECK-NEXT: TBNZW %op, 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
successors: %bb.2, %bb.3
liveins: $w0, $w1
@@ -144,14 +156,17 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: condbr_of_shl
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: %lhs:gpr32 = COPY $w0
- ; CHECK: %op:gpr32 = UBFMWri %lhs, 31, 30
- ; CHECK: TBNZW %op, 0, %bb.2
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %lhs:gpr32 = COPY $w0
+ ; CHECK-NEXT: %op:gpr32 = UBFMWri %lhs, 31, 30
+ ; CHECK-NEXT: TBNZW %op, 0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
; We won't ever fold this, because
; bit = 0
; bit - constant < 0, which isn't valid for tbz/tbnz.
@@ -179,13 +194,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: condbr_of_ashr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: %lhs:gpr32 = COPY $w0
- ; CHECK: TBNZW %lhs, 1, %bb.2
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %lhs:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %lhs, 1, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
; We can fold ashr, because we can have
;
; (tbz (ashr x, c), 0) where 0 + c > # bits in x.
@@ -213,13 +231,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: tbnzx
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: %lhs:gpr64 = COPY $x0
- ; CHECK: TBNZX %lhs, 63, %bb.2
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %lhs:gpr64 = COPY $x0
+ ; CHECK-NEXT: TBNZX %lhs, 63, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
successors: %bb.2, %bb.3
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
index f7b78b1e0f094..754cb341d979e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
@@ -9,11 +9,13 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: cbz_s32
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: CBZW [[COPY]], %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: CBZW [[COPY]], %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
bb.0:
liveins: $w0
successors: %bb.0, %bb.1
@@ -36,11 +38,13 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: cbz_s64
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: CBZX [[COPY]], %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: CBZX [[COPY]], %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
bb.0:
liveins: $x0
successors: %bb.0, %bb.1
@@ -63,11 +67,13 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: cbnz_s32
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: CBNZW [[COPY]], %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: CBNZW [[COPY]], %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
bb.0:
liveins: $w0
successors: %bb.0, %bb.1
@@ -90,11 +96,13 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: cbnz_s64
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: CBNZX [[COPY]], %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: CBNZX [[COPY]], %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
bb.0:
liveins: $x0
successors: %bb.0, %bb.1
@@ -117,15 +125,19 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_rhs_inttoptr
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
- ; CHECK: CBZX [[COPY]], %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: STRXui $xzr, [[COPY]], 0 :: (store (s64))
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: CBZX [[COPY]], %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64))
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
successors: %bb.2, %bb.3
liveins: $x0
@@ -154,17 +166,21 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_rhs_unknown
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load (s64))
- ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: STRXui $xzr, [[COPY]], 0 :: (store (s64))
- ; CHECK: bb.2:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load (s64))
+ ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64))
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
successors: %bb.2, %bb.3
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index c967d9486c8cf..a0a972fff48d0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -27,7 +27,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: inttoptr_p0_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
- ; CHECK: $x0 = COPY [[COPY]]
+ ; CHECK-NEXT: $x0 = COPY [[COPY]]
%0(s64) = COPY $x0
%1(p0) = G_INTTOPTR %0
$x0 = COPY %1(p0)
@@ -46,7 +46,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s64_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: $x0 = COPY [[COPY]]
+ ; CHECK-NEXT: $x0 = COPY [[COPY]]
%0(p0) = COPY $x0
%1(s64) = G_PTRTOINT %0
$x0 = COPY %1(s64)
@@ -65,8 +65,8 @@ body: |
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s32_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
%1(s32) = G_PTRTOINT %0
$w0 = COPY %1(s32)
@@ -85,9 +85,9 @@ body: |
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s16_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
- ; CHECK: $w0 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY2]]
%0(p0) = COPY $x0
%1(s16) = G_PTRTOINT %0
%2:gpr(s32) = G_ANYEXT %1
@@ -107,9 +107,9 @@ body: |
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s8_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
- ; CHECK: $w0 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY2]]
%0(p0) = COPY $x0
%1(s8) = G_PTRTOINT %0
%2:gpr(s32) = G_ANYEXT %1
@@ -129,9 +129,9 @@ body: |
liveins: $x0
; CHECK-LABEL: name: ptrtoint_s1_p0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
- ; CHECK: $w0 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY2]]
%0(p0) = COPY $x0
%1(s1) = G_PTRTOINT %0
%2:gpr(s32) = G_ANYEXT %1
@@ -148,10 +148,11 @@ body: |
liveins: $q0, $x0
; CHECK-LABEL: name: inttoptr_v2p0_v2s64
; CHECK: liveins: $q0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
- ; CHECK: $x0 = COPY [[COPY1]]
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
+ ; CHECK-NEXT: $x0 = COPY [[COPY1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%1:fpr(<2 x s64>) = COPY $q0
%2:fpr(<2 x p0>) = G_INTTOPTR %1(<2 x s64>)
%4:gpr(s64) = G_CONSTANT i64 0
@@ -170,9 +171,10 @@ body: |
liveins: $q0
; CHECK-LABEL: name: ptrtoint_v2s64_v2p0
; CHECK: liveins: $q0
- ; CHECK: %ptr:fpr128 = COPY $q0
- ; CHECK: $q0 = COPY %ptr
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:fpr128 = COPY $q0
+ ; CHECK-NEXT: $q0 = COPY %ptr
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%ptr:fpr(<2 x p0>) = COPY $q0
%int:fpr(<2 x s64>) = G_PTRTOINT %ptr(<2 x p0>)
$q0 = COPY %int(<2 x s64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
index 1aec09b69680b..28160398af28f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
@@ -22,29 +22,34 @@ jumpTable:
body: |
; CHECK-LABEL: name: check_constrain
; CHECK: bb.0:
- ; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
- ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv
- ; CHECK: Bcc 8, %bb.3, implicit $nzcv
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
- ; CHECK: early-clobber %6:gpr64, early-clobber %7:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
- ; CHECK: BR %6
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: B %bb.3
- ; CHECK: bb.3:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
+ ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 8, %bb.3, implicit $nzcv
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
+ ; CHECK-NEXT: early-clobber %5:gpr64, early-clobber %6:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
+ ; CHECK-NEXT: BR %5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: RET_ReallyLR
bb.1:
%1:gpr(p0) = G_IMPLICIT_DEF
%5:gpr(s64) = G_ZEXTLOAD %1(p0) :: (load (s8))
%7:gpr(s64) = G_CONSTANT i64 8
%16:gpr(s32) = G_ICMP intpred(ugt), %5(s64), %7
- %8:gpr(s1) = G_TRUNC %16(s32)
- G_BRCOND %8(s1), %bb.4
+ G_BRCOND %16, %bb.4
bb.2:
successors: %bb.3, %bb.4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
index b8c9a6c881da7..0a6bf8d5e538a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
@@ -54,32 +54,40 @@ jumpTable:
body: |
; CHECK-LABEL: name: jt_test
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
- ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
- ; CHECK: Bcc 8, %bb.4, implicit $nzcv
- ; CHECK: bb.1.entry:
- ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
- ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
- ; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
- ; CHECK: BR %18
- ; CHECK: bb.2.sw.bb:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = nsw ADDWri [[COPY]], 42, 0
- ; CHECK: B %bb.4
- ; CHECK: bb.3.sw.bb1:
- ; CHECK: successors: %bb.4(0x80000000)
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
- ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[COPY]], [[MOVi32imm]], $wzr
- ; CHECK: bb.4.return:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[COPY1]], %bb.0, [[COPY2]], %bb.1
- ; CHECK: $w0 = COPY [[PHI]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
+ ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 8, %bb.4, implicit $nzcv
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.entry:
+ ; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
+ ; CHECK-NEXT: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
+ ; CHECK-NEXT: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
+ ; CHECK-NEXT: BR %18
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.sw.bb:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = nsw ADDWri [[COPY]], 42, 0
+ ; CHECK-NEXT: B %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.sw.bb1:
+ ; CHECK-NEXT: successors: %bb.4(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
+ ; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[COPY]], [[MOVi32imm]], $wzr
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.return:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[COPY1]], %bb.0, [[COPY2]], %bb.1
+ ; CHECK-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.1.entry:
liveins: $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
index f313e08178dbb..14ccb00ec986d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -58,8 +58,8 @@ body: |
; CHECK-LABEL: name: load_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load (s64) from %ir.addr)
- ; CHECK: $x0 = COPY [[LDRXui]]
+ ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: $x0 = COPY [[LDRXui]]
%0(p0) = COPY $x0
%1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)
$x0 = COPY %1(s64)
@@ -80,8 +80,8 @@ body: |
; CHECK-LABEL: name: load_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from %ir.addr)
- ; CHECK: $w0 = COPY [[LDRWui]]
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRWui]]
%0(p0) = COPY $x0
%1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
$w0 = COPY %1(s32)
@@ -98,8 +98,8 @@ body: |
; CHECK-LABEL: name: load_s16_gpr_anyext
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
- ; CHECK: $w0 = COPY [[LDRHHui]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_LOAD %0 :: (load (s16) from %ir.addr)
$w0 = COPY %1(s32)
@@ -120,9 +120,9 @@ body: |
; CHECK-LABEL: name: load_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
%1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
@@ -140,8 +140,8 @@ body: |
; CHECK-LABEL: name: load_s8_gpr_anyext
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
- ; CHECK: $w0 = COPY [[LDRBBui]]
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_LOAD %0 :: (load (s8) from %ir.addr)
$w0 = COPY %1(s32)
@@ -162,9 +162,9 @@ body: |
; CHECK-LABEL: name: load_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
%1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
@@ -189,7 +189,7 @@ body: |
; CHECK-LABEL: name: load_fi_s64_gpr
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load (s64))
- ; CHECK: $x0 = COPY [[LDRXui]]
+ ; CHECK-NEXT: $x0 = COPY [[LDRXui]]
%0(p0) = G_FRAME_INDEX %stack.0.ptr0
%1(s64) = G_LOAD %0 :: (load (s64))
$x0 = COPY %1(s64)
@@ -212,8 +212,8 @@ body: |
; CHECK-LABEL: name: load_gep_128_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load (s64) from %ir.addr)
- ; CHECK: $x0 = COPY [[LDRXui]]
+ ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: $x0 = COPY [[LDRXui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 128
%2(p0) = G_PTR_ADD %0, %1
@@ -238,8 +238,8 @@ body: |
; CHECK-LABEL: name: load_gep_512_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load (s32) from %ir.addr)
- ; CHECK: $w0 = COPY [[LDRWui]]
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRWui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 512
%2(p0) = G_PTR_ADD %0, %1
@@ -264,9 +264,9 @@ body: |
; CHECK-LABEL: name: load_gep_64_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (s16) from %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 64
%2(p0) = G_PTR_ADD %0, %1
@@ -292,9 +292,9 @@ body: |
; CHECK-LABEL: name: load_gep_1_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (s8) from %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 1
%2(p0) = G_PTR_ADD %0, %1
@@ -318,8 +318,8 @@ body: |
; CHECK-LABEL: name: load_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (s64) from %ir.addr)
- ; CHECK: $d0 = COPY [[LDRDui]]
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
%1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)
$d0 = COPY %1(s64)
@@ -340,8 +340,8 @@ body: |
; CHECK-LABEL: name: load_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load (s32) from %ir.addr)
- ; CHECK: $s0 = COPY [[LDRSui]]
+ ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: $s0 = COPY [[LDRSui]]
%0(p0) = COPY $x0
%1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
$s0 = COPY %1(s32)
@@ -362,8 +362,8 @@ body: |
; CHECK-LABEL: name: load_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16) from %ir.addr)
- ; CHECK: $h0 = COPY [[LDRHui]]
+ ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: $h0 = COPY [[LDRHui]]
%0(p0) = COPY $x0
%1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)
$h0 = COPY %1(s16)
@@ -384,8 +384,8 @@ body: |
; CHECK-LABEL: name: load_s8_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8) from %ir.addr)
- ; CHECK: $b0 = COPY [[LDRBui]]
+ ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: $b0 = COPY [[LDRBui]]
%0(p0) = COPY $x0
%1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
$b0 = COPY %1(s8)
@@ -408,8 +408,8 @@ body: |
; CHECK-LABEL: name: load_gep_8_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load (s64) from %ir.addr)
- ; CHECK: $d0 = COPY [[LDRDui]]
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load (s64) from %ir.addr)
+ ; CHECK-NEXT: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 8
%2(p0) = G_PTR_ADD %0, %1
@@ -434,8 +434,8 @@ body: |
; CHECK-LABEL: name: load_gep_16_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load (s32) from %ir.addr)
- ; CHECK: $s0 = COPY [[LDRSui]]
+ ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load (s32) from %ir.addr)
+ ; CHECK-NEXT: $s0 = COPY [[LDRSui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 16
%2(p0) = G_PTR_ADD %0, %1
@@ -460,8 +460,8 @@ body: |
; CHECK-LABEL: name: load_gep_64_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load (s16) from %ir.addr)
- ; CHECK: $h0 = COPY [[LDRHui]]
+ ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: $h0 = COPY [[LDRHui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 64
%2(p0) = G_PTR_ADD %0, %1
@@ -486,8 +486,8 @@ body: |
; CHECK-LABEL: name: load_gep_32_s8_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load (s8) from %ir.addr)
- ; CHECK: $b0 = COPY [[LDRBui]]
+ ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: $b0 = COPY [[LDRBui]]
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 32
%2(p0) = G_PTR_ADD %0, %1
@@ -509,8 +509,8 @@ body: |
; CHECK-LABEL: name: load_v2s32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>) from %ir.addr)
- ; CHECK: $d0 = COPY [[LDRDui]]
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>) from %ir.addr)
+ ; CHECK-NEXT: $d0 = COPY [[LDRDui]]
%0(p0) = COPY $x0
%1(<2 x s32>) = G_LOAD %0 :: (load (<2 x s32>) from %ir.addr)
$d0 = COPY %1(<2 x s32>)
@@ -530,8 +530,8 @@ body: |
; CHECK-LABEL: name: load_v2s64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>) from %ir.addr)
- ; CHECK: $q0 = COPY [[LDRQui]]
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>) from %ir.addr)
+ ; CHECK-NEXT: $q0 = COPY [[LDRQui]]
%0(p0) = COPY $x0
%1(<2 x s64>) = G_LOAD %0 :: (load (<2 x s64>) from %ir.addr)
$q0 = COPY %1(<2 x s64>)
@@ -552,10 +552,11 @@ body: |
; CHECK-LABEL: name: load_4xi16
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<4 x s16>) from %ir.ptr)
- ; CHECK: $d0 = COPY [[LDRDui]]
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<4 x s16>) from %ir.ptr)
+ ; CHECK-NEXT: $d0 = COPY [[LDRDui]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:gpr(p0) = COPY $x0
%1:fpr(<4 x s16>) = G_LOAD %0(p0) :: (load (<4 x s16>) from %ir.ptr)
$d0 = COPY %1(<4 x s16>)
@@ -578,10 +579,11 @@ body: |
; CHECK-LABEL: name: load_4xi32
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>) from %ir.ptr)
- ; CHECK: $q0 = COPY [[LDRQui]]
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>) from %ir.ptr)
+ ; CHECK-NEXT: $q0 = COPY [[LDRQui]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
%1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.ptr)
$q0 = COPY %1(<4 x s32>)
@@ -604,10 +606,11 @@ body: |
; CHECK-LABEL: name: load_8xi16
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>) from %ir.ptr)
- ; CHECK: $q0 = COPY [[LDRQui]]
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>) from %ir.ptr)
+ ; CHECK-NEXT: $q0 = COPY [[LDRQui]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
%1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.ptr)
$q0 = COPY %1(<8 x s16>)
@@ -630,10 +633,11 @@ body: |
; CHECK-LABEL: name: load_16xi8
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>) from %ir.ptr)
- ; CHECK: $q0 = COPY [[LDRQui]]
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>) from %ir.ptr)
+ ; CHECK-NEXT: $q0 = COPY [[LDRQui]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
%1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.ptr)
$q0 = COPY %1(<16 x s8>)
@@ -660,12 +664,13 @@ body: |
; CHECK-LABEL: name: anyext_on_fpr
; CHECK: liveins: $w3, $x0, $x1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16))
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRHui]], %subreg.hsub
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
- ; CHECK: $w0 = COPY [[COPY1]]
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRHui]], %subreg.hsub
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%16:fpr(s32) = G_LOAD %0(p0) :: (load (s16))
%24:gpr(s32) = COPY %16(s32)
@@ -693,12 +698,13 @@ body: |
; CHECK-LABEL: name: anyext_on_fpr8
; CHECK: liveins: $w3, $x0, $x1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRBui]], %subreg.bsub
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
- ; CHECK: $w0 = COPY [[COPY1]]
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRBui]], %subreg.bsub
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%16:fpr(s32) = G_LOAD %0(p0) :: (load (s8))
%24:gpr(s32) = COPY %16(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
index 135799d837296..dc7c975edb488 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
@@ -11,11 +11,12 @@ body: |
; CHECK-LABEL: name: redundant_zext_8
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
- ; CHECK: $w0 = COPY [[COPY1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(p0) = COPY $x0
%2:gpr(s8) = G_LOAD %1(p0) :: (load (s8))
%3:gpr(s32) = G_ZEXT %2(s8)
@@ -34,11 +35,12 @@ body: |
; CHECK-LABEL: name: redundant_zext_16
; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK: $w0 = COPY [[COPY1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(p0) = COPY $x0
%2:gpr(s16) = G_LOAD %1(p0) :: (load (s16))
%3:gpr(s32) = G_ZEXT %2(s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
index 39f2dc45525a1..34b4360f51efe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
@@ -14,14 +14,15 @@ body: |
; CHECK-LABEL: name: saddo_s32
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%3:gpr(s32), %4:gpr(s1) = G_SADDO %0, %1
@@ -43,14 +44,15 @@ body: |
; CHECK-LABEL: name: saddo_s64
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%3:gpr(s64), %4:gpr(s1) = G_SADDO %0, %1
@@ -73,11 +75,12 @@ body: |
;
; CHECK-LABEL: name: saddo_s32_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 16
%add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy, %constant
@@ -98,12 +101,13 @@ body: |
;
; CHECK-LABEL: name: saddo_s32_shifted
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy1:gpr32 = COPY $w0
- ; CHECK: %copy2:gpr32 = COPY $w1
- ; CHECK: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %copy2:gpr32 = COPY $w1
+ ; CHECK-NEXT: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy1:gpr(s32) = COPY $w0
%copy2:gpr(s32) = COPY $w1
%constant:gpr(s32) = G_CONSTANT i32 16
@@ -126,11 +130,12 @@ body: |
;
; CHECK-LABEL: name: saddo_s32_neg_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 -16
%add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy, %constant
@@ -150,12 +155,13 @@ body: |
; Check that we get ADDSXrx.
; CHECK-LABEL: name: saddo_arith_extended
; CHECK: liveins: $w0, $x0
- ; CHECK: %reg0:gpr64sp = COPY $x0
- ; CHECK: %reg1:gpr32 = COPY $w0
- ; CHECK: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
- ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $x0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
+ ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%reg1:gpr(s32) = COPY $w0
%ext:gpr(s64) = G_ZEXT %reg1(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
index 7800e478a8bc6..c943ffd48b929 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
@@ -15,15 +15,16 @@ body: |
; CHECK-LABEL: name: select_f32
; CHECK: liveins: $s0, $s1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
- ; CHECK: $s0 = COPY [[FCSELSrrr]]
- ; CHECK: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
+ ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
%3:gpr(s32) = COPY $w0
%0:gpr(s1) = G_TRUNC %3(s32)
%1:fpr(s32) = COPY $s0
@@ -47,15 +48,16 @@ body: |
; CHECK-LABEL: name: select_f64
; CHECK: liveins: $d0, $d1, $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
- ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
- ; CHECK: $d0 = COPY [[FCSELDrrr]]
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
+ ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
%3:gpr(s32) = COPY $w0
%0:gpr(s1) = G_TRUNC %3(s32)
%1:fpr(s64) = COPY $d0
@@ -75,14 +77,15 @@ body: |
liveins: $w0, $w1, $w2, $w3
; CHECK-LABEL: name: csel
; CHECK: liveins: $w0, $w1, $w2, $w3
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %t:gpr32 = COPY $w2
- ; CHECK: %f:gpr32 = COPY $w3
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %t:gpr32 = COPY $w2
+ ; CHECK-NEXT: %f:gpr32 = COPY $w3
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
@@ -105,12 +108,13 @@ body: |
; CHECK-LABEL: name: csinc_t_0_f_1
; CHECK: liveins: $w0, $w1
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
@@ -133,12 +137,13 @@ body: |
; CHECK-LABEL: name: csinv_t_0_f_neg_1
; CHECK: liveins: $w0, $w1
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
@@ -161,13 +166,14 @@ body: |
; CHECK-LABEL: name: csinc_t_1
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %f:gpr32 = COPY $w2
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %f:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
@@ -190,13 +196,14 @@ body: |
; CHECK-LABEL: name: csinv_t_neg_1
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %f:gpr32 = COPY $w2
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %f:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
@@ -219,13 +226,14 @@ body: |
; CHECK-LABEL: name: csinc_f_1
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %t:gpr32 = COPY $w2
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %t:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
@@ -248,13 +256,14 @@ body: |
; CHECK-LABEL: name: csinc_f_neg_1
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %t:gpr32 = COPY $w2
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %t:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
@@ -277,12 +286,13 @@ body: |
; CHECK-LABEL: name: csinc_t_1_no_cmp
; CHECK: liveins: $w0, $w1
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %f:gpr32 = COPY $w1
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %f:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%cond:gpr(s1) = G_TRUNC %reg0(s32)
%t:gpr(s32) = G_CONSTANT i32 1
@@ -304,12 +314,13 @@ body: |
; CHECK-LABEL: name: csinc_f_1_no_cmp
; CHECK: liveins: $w0, $w1
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %t:gpr32 = COPY $w1
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %t:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%cond:gpr(s1) = G_TRUNC %reg0(s32)
%t:gpr(s32) = COPY $w1
@@ -331,13 +342,14 @@ body: |
; CHECK-LABEL: name: csinc_t_1_no_cmp_s64
; CHECK: liveins: $x0, $x1
- ; CHECK: %reg0:gpr64 = COPY $x0
- ; CHECK: %cond:gpr32 = COPY %reg0.sub_32
- ; CHECK: %f:gpr64 = COPY $x1
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
- ; CHECK: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv
- ; CHECK: $x0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+ ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+ ; CHECK-NEXT: %f:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%cond:gpr(s1) = G_TRUNC %reg0(s64)
%t:gpr(s64) = G_CONSTANT i64 1
@@ -359,13 +371,14 @@ body: |
; CHECK-LABEL: name: csneg_s32
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %t:gpr32 = COPY $w2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSNEGWr %t, %reg1, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %t:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg1, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%cond:gpr(s1) = G_TRUNC %reg0(s32)
%reg1:gpr(s32) = COPY $w1
@@ -389,13 +402,14 @@ body: |
; CHECK-LABEL: name: csneg_inverted_cc
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %f:gpr32 = COPY $w2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %f:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%cond:gpr(s1) = G_TRUNC %reg0(s32)
%reg1:gpr(s32) = COPY $w1
@@ -419,14 +433,15 @@ body: |
; CHECK-LABEL: name: csneg_s64
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: %reg0:gpr64 = COPY $x0
- ; CHECK: %cond:gpr32 = COPY %reg0.sub_32
- ; CHECK: %reg1:gpr64 = COPY $x1
- ; CHECK: %t:gpr64 = COPY $x2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
- ; CHECK: %select:gpr64 = CSNEGXr %t, %reg1, 1, implicit $nzcv
- ; CHECK: $x0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+ ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+ ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
+ ; CHECK-NEXT: %t:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr64 = CSNEGXr %t, %reg1, 1, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%cond:gpr(s1) = G_TRUNC %reg0(s64)
%reg1:gpr(s64) = COPY $x1
@@ -450,13 +465,14 @@ body: |
; CHECK-LABEL: name: csneg_with_true_cst
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %t:gpr32 = MOVi32imm 1
- ; CHECK: %reg2:gpr32 = COPY $w2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %t:gpr32 = MOVi32imm 1
+ ; CHECK-NEXT: %reg2:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%cond:gpr(s1) = G_TRUNC %reg0(s32)
%reg1:gpr(s32) = COPY $w1
@@ -480,13 +496,14 @@ body: |
; CHECK-LABEL: name: csinv_s32
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %t:gpr32 = COPY $w2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINVWr %t, %reg1, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %t:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, %reg1, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cond:gpr(s1) = G_TRUNC %reg0(s32)
@@ -510,13 +527,14 @@ body: |
; CHECK-LABEL: name: csinv_inverted_cc
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %f:gpr32 = COPY $w2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %f:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cond:gpr(s1) = G_TRUNC %reg0(s32)
@@ -540,14 +558,15 @@ body: |
; CHECK-LABEL: name: csinv_s64
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: %reg0:gpr64 = COPY $x0
- ; CHECK: %reg1:gpr64 = COPY $x1
- ; CHECK: %cond:gpr32 = COPY %reg0.sub_32
- ; CHECK: %t:gpr64 = COPY $x2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
- ; CHECK: %select:gpr64 = CSINVXr %t, %reg1, 1, implicit $nzcv
- ; CHECK: $x0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+ ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
+ ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+ ; CHECK-NEXT: %t:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr64 = CSINVXr %t, %reg1, 1, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%reg1:gpr(s64) = COPY $x1
%cond:gpr(s1) = G_TRUNC %reg0(s64)
@@ -571,17 +590,18 @@ body: |
; CHECK-LABEL: name: xor_not_negative_one
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: %reg0:gpr64 = COPY $x0
- ; CHECK: %reg1:gpr64 = COPY $x1
- ; CHECK: %cond:gpr32 = COPY %reg0.sub_32
- ; CHECK: %t:gpr64 = COPY $x2
- ; CHECK: %negative_one:gpr32 = MOVi32imm -1
- ; CHECK: %zext:gpr64 = SUBREG_TO_REG 0, %negative_one, %subreg.sub_32
- ; CHECK: %xor:gpr64 = EORXrr %reg1, %zext
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
- ; CHECK: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv
- ; CHECK: $x0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+ ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
+ ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+ ; CHECK-NEXT: %t:gpr64 = COPY $x2
+ ; CHECK-NEXT: %negative_one:gpr32 = MOVi32imm -1
+ ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, %negative_one, %subreg.sub_32
+ ; CHECK-NEXT: %xor:gpr64 = EORXrr %reg1, %zext
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%reg1:gpr(s64) = COPY $x1
%cond:gpr(s1) = G_TRUNC %reg0(s64)
@@ -605,13 +625,14 @@ body: |
; G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc
; CHECK-LABEL: name: csinc_s32
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %t:gpr32 = COPY $w2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %t:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cond:gpr(s1) = G_TRUNC %reg0(s32)
@@ -634,13 +655,14 @@ body: |
; G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc
; CHECK-LABEL: name: csinc_s32_inverted_cc
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %f:gpr32 = COPY $w2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %f:gpr32 = COPY $w2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%cond:gpr(s1) = G_TRUNC %reg0(s32)
@@ -664,14 +686,15 @@ body: |
; CHECK-LABEL: name: csinc_ptr_add
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: %reg0:gpr64 = COPY $x0
- ; CHECK: %reg1:gpr64 = COPY $x1
- ; CHECK: %cond:gpr32 = COPY %reg0.sub_32
- ; CHECK: %t:gpr64 = COPY $x2
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
- ; CHECK: %select:gpr64 = CSINCXr %t, %reg1, 1, implicit $nzcv
- ; CHECK: $x0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64 = COPY $x0
+ ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
+ ; CHECK-NEXT: %cond:gpr32 = COPY %reg0.sub_32
+ ; CHECK-NEXT: %t:gpr64 = COPY $x2
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr64 = CSINCXr %t, %reg1, 1, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%reg1:gpr(p0) = COPY $x1
%cond:gpr(s1) = G_TRUNC %reg0(s64)
@@ -693,14 +716,15 @@ body: |
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: binop_dont_optimize_twice
; CHECK: liveins: $w0, $w1, $w2
- ; CHECK: %reg0:gpr32 = COPY $w0
- ; CHECK: %reg1:gpr32 = COPY $w1
- ; CHECK: %reg2:gpr32 = COPY $w2
- ; CHECK: %xor:gpr32 = ORNWrr $wzr, %reg1
- ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
- ; CHECK: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv
- ; CHECK: $w0 = COPY %select
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
+ ; CHECK-NEXT: %reg2:gpr32 = COPY $w2
+ ; CHECK-NEXT: %xor:gpr32 = ORNWrr $wzr, %reg1
+ ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %select
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%reg0:gpr(s32) = COPY $w0
%reg1:gpr(s32) = COPY $w1
%reg2:gpr(s32) = COPY $w2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
index 639776a7ecbd5..1d6ec355c3d18 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
@@ -14,14 +14,15 @@ body: |
; CHECK-LABEL: name: ssubo_s32
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%3:gpr(s32), %4:gpr(s1) = G_SSUBO %0, %1
@@ -43,14 +44,15 @@ body: |
; CHECK-LABEL: name: ssubo_s64
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%3:gpr(s64), %4:gpr(s1) = G_SSUBO %0, %1
@@ -73,11 +75,12 @@ body: |
;
; CHECK-LABEL: name: ssubo_s32_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 16
%add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant
@@ -98,12 +101,13 @@ body: |
;
; CHECK-LABEL: name: ssubo_s32_shifted
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy1:gpr32 = COPY $w0
- ; CHECK: %copy2:gpr32 = COPY $w1
- ; CHECK: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %copy2:gpr32 = COPY $w1
+ ; CHECK-NEXT: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy1:gpr(s32) = COPY $w0
%copy2:gpr(s32) = COPY $w1
%constant:gpr(s32) = G_CONSTANT i32 16
@@ -126,11 +130,12 @@ body: |
;
; CHECK-LABEL: name: ssubo_s32_neg_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 -16
%add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant
@@ -150,12 +155,13 @@ body: |
; Check that we get ADDSXrx.
; CHECK-LABEL: name: ssubo_arith_extended
; CHECK: liveins: $w0, $x0
- ; CHECK: %reg0:gpr64sp = COPY $x0
- ; CHECK: %reg1:gpr32 = COPY $w0
- ; CHECK: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
- ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
- ; CHECK: $x0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
+ ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%reg1:gpr(s32) = COPY $w0
%ext:gpr(s64) = G_ZEXT %reg1(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
index 38bfa9eee8a64..88a01f043586f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -62,8 +62,8 @@ body: |
; CHECK-LABEL: name: store_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK: STRXui [[COPY1]], [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: STRXui [[COPY1]], [[COPY]], 0 :: (store (s64) into %ir.addr)
%0(p0) = COPY $x0
%1(s64) = COPY $x1
G_STORE %1, %0 :: (store (s64) into %ir.addr)
@@ -85,8 +85,8 @@ body: |
; CHECK-LABEL: name: store_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: STRWui [[COPY1]], [[COPY]], 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: STRWui [[COPY1]], [[COPY]], 0 :: (store (s32) into %ir.addr)
%0(p0) = COPY $x0
%1(s32) = COPY $w1
G_STORE %1, %0 :: (store (s32) into %ir.addr)
@@ -108,8 +108,8 @@ body: |
; CHECK-LABEL: name: store_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store (s16) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 0 :: (store (s16) into %ir.addr)
%0(p0) = COPY $x0
%2:gpr(s32) = COPY $w1
%1(s16) = G_TRUNC %2
@@ -132,8 +132,8 @@ body: |
; CHECK-LABEL: name: store_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store (s8) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: STRBBui [[COPY1]], [[COPY]], 0 :: (store (s8) into %ir.addr)
%0(p0) = COPY $x0
%2:gpr(s32) = COPY $w1
%1(s8) = G_TRUNC %2
@@ -156,7 +156,7 @@ body: |
; CHECK-LABEL: name: store_zero_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRXui $xzr, [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64) into %ir.addr)
%0(p0) = COPY $x0
%1(s64) = G_CONSTANT i64 0
G_STORE %1, %0 :: (store (s64) into %ir.addr)
@@ -178,7 +178,7 @@ body: |
; CHECK-LABEL: name: store_zero_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRWui $wzr, [[COPY]], 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: STRWui $wzr, [[COPY]], 0 :: (store (s32) into %ir.addr)
%0(p0) = COPY $x0
%1(s32) = G_CONSTANT i32 0
G_STORE %1, %0 :: (store (s32) into %ir.addr)
@@ -194,7 +194,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_zero_s16
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRHHui $wzr, [[COPY]], 0 :: (store (s16))
+ ; CHECK-NEXT: STRHHui $wzr, [[COPY]], 0 :: (store (s16))
%0:gpr(p0) = COPY $x0
%1:gpr(s16) = G_CONSTANT i16 0
G_STORE %1(s16), %0(p0) :: (store (s16))
@@ -210,7 +210,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_zero_s8
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRBBui $wzr, [[COPY]], 0 :: (store (s8))
+ ; CHECK-NEXT: STRBBui $wzr, [[COPY]], 0 :: (store (s8))
%0:gpr(p0) = COPY $x0
%1:gpr(s8) = G_CONSTANT i8 0
G_STORE %1(s8), %0(p0) :: (store (s8))
@@ -225,7 +225,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_zero_look_through_cst
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRXui $xzr, [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: STRXui $xzr, [[COPY]], 0 :: (store (s64) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(s32) = G_CONSTANT i32 0
%2:gpr(s64) = G_ZEXT %1
@@ -250,8 +250,8 @@ body: |
; CHECK-LABEL: name: store_fi_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
- ; CHECK: STRXui [[COPY1]], %stack.0.ptr0, 0 :: (store (p0))
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+ ; CHECK-NEXT: STRXui [[COPY1]], %stack.0.ptr0, 0 :: (store (p0))
%0(p0) = COPY $x0
%1(p0) = G_FRAME_INDEX %stack.0.ptr0
G_STORE %0, %1 :: (store (p0))
@@ -274,8 +274,8 @@ body: |
; CHECK-LABEL: name: store_gep_128_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK: STRXui [[COPY1]], [[COPY]], 16 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: STRXui [[COPY1]], [[COPY]], 16 :: (store (s64) into %ir.addr)
%0(p0) = COPY $x0
%1(s64) = COPY $x1
%2(s64) = G_CONSTANT i64 128
@@ -300,8 +300,8 @@ body: |
; CHECK-LABEL: name: store_gep_512_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: STRWui [[COPY1]], [[COPY]], 128 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: STRWui [[COPY1]], [[COPY]], 128 :: (store (s32) into %ir.addr)
%0(p0) = COPY $x0
%1(s32) = COPY $w1
%2(s64) = G_CONSTANT i64 512
@@ -326,8 +326,8 @@ body: |
; CHECK-LABEL: name: store_gep_64_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store (s16) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 32 :: (store (s16) into %ir.addr)
%0(p0) = COPY $x0
%4:gpr(s32) = COPY $w1
%1(s16) = G_TRUNC %4
@@ -353,8 +353,8 @@ body: |
; CHECK-LABEL: name: store_gep_1_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store (s8) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: STRBBui [[COPY1]], [[COPY]], 1 :: (store (s8) into %ir.addr)
%0(p0) = COPY $x0
%4:gpr(s32) = COPY $w1
%1(s8) = G_TRUNC %4
@@ -378,8 +378,8 @@ body: |
; CHECK-LABEL: name: store_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (s64) into %ir.addr)
%0(p0) = COPY $x0
%1(s64) = COPY $d1
G_STORE %1, %0 :: (store (s64) into %ir.addr)
@@ -401,8 +401,8 @@ body: |
; CHECK-LABEL: name: store_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: STRSui [[COPY1]], [[COPY]], 0 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: STRSui [[COPY1]], [[COPY]], 0 :: (store (s32) into %ir.addr)
%0(p0) = COPY $x0
%1(s32) = COPY $s1
G_STORE %1, %0 :: (store (s32) into %ir.addr)
@@ -426,8 +426,8 @@ body: |
; CHECK-LABEL: name: store_gep_8_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: STRDui [[COPY1]], [[COPY]], 1 :: (store (s64) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 1 :: (store (s64) into %ir.addr)
%0(p0) = COPY $x0
%1(s64) = COPY $d1
%2(s64) = G_CONSTANT i64 8
@@ -452,8 +452,8 @@ body: |
; CHECK-LABEL: name: store_gep_8_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: STRSui [[COPY1]], [[COPY]], 2 :: (store (s32) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+ ; CHECK-NEXT: STRSui [[COPY1]], [[COPY]], 2 :: (store (s32) into %ir.addr)
%0(p0) = COPY $x0
%1(s32) = COPY $s1
%2(s64) = G_CONSTANT i64 8
@@ -475,8 +475,8 @@ body: |
; CHECK-LABEL: name: store_v2s32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store (<2 x s32>) into %ir.addr)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: STRDui [[COPY1]], [[COPY]], 0 :: (store (<2 x s32>) into %ir.addr)
%0(p0) = COPY $x0
%1(<2 x s32>) = COPY $d1
G_STORE %1, %0 :: (store (<2 x s32>) into %ir.addr)
@@ -496,8 +496,8 @@ body: |
liveins: $x0, $d1
; CHECK-LABEL: name: store_v2s64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
- ; CHECK: STRQui [[COPY1]], [[COPY]], 0 :: (store (<2 x s64>) into %ir.addr, align 8)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+ ; CHECK-NEXT: STRQui [[COPY1]], [[COPY]], 0 :: (store (<2 x s64>) into %ir.addr, align 8)
%0(p0) = COPY $x0
%1(<2 x s64>) = COPY $q1
G_STORE %1, %0 :: (store (<2 x s64>) into %ir.addr, align 8)
@@ -519,10 +519,11 @@ body: |
; CHECK-LABEL: name: store_4xi16
; CHECK: liveins: $d0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRDui [[COPY]], [[COPY1]], 0 :: (store (<4 x s16>) into %ir.ptr)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: STRDui [[COPY]], [[COPY1]], 0 :: (store (<4 x s16>) into %ir.ptr)
+ ; CHECK-NEXT: RET_ReallyLR
%0:fpr(<4 x s16>) = COPY $d0
%1:gpr(p0) = COPY $x0
G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>) into %ir.ptr)
@@ -545,10 +546,11 @@ body: |
; CHECK-LABEL: name: store_4xi32
; CHECK: liveins: $q0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store (<4 x s32>) into %ir.ptr)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<4 x s32>) into %ir.ptr)
+ ; CHECK-NEXT: RET_ReallyLR
%0:fpr(<4 x s32>) = COPY $q0
%1:gpr(p0) = COPY $x0
G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.ptr)
@@ -571,10 +573,11 @@ body: |
; CHECK-LABEL: name: store_8xi16
; CHECK: liveins: $q0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store (<8 x s16>) into %ir.ptr)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<8 x s16>) into %ir.ptr)
+ ; CHECK-NEXT: RET_ReallyLR
%0:fpr(<8 x s16>) = COPY $q0
%1:gpr(p0) = COPY $x0
G_STORE %0(<8 x s16>), %1(p0) :: (store (<8 x s16>) into %ir.ptr)
@@ -597,10 +600,11 @@ body: |
; CHECK-LABEL: name: store_16xi8
; CHECK: liveins: $q0, $x0
- ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store (<16 x s8>) into %ir.ptr)
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK-NEXT: STRQui [[COPY]], [[COPY1]], 0 :: (store (<16 x s8>) into %ir.ptr)
+ ; CHECK-NEXT: RET_ReallyLR
%0:fpr(<16 x s8>) = COPY $q0
%1:gpr(p0) = COPY $x0
G_STORE %0(<16 x s8>), %1(p0) :: (store (<16 x s8>) into %ir.ptr)
@@ -617,10 +621,11 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_adrp_add_low
; CHECK: liveins: $x0
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
- ; CHECK: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store (p0) into @x)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
+ ; CHECK-NEXT: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store (p0) into @x)
%copy:gpr(p0) = COPY $x0
%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x
%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
@@ -637,10 +642,11 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_adrp_add_low_foldable_offset
; CHECK: liveins: $x0
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x + 8
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
- ; CHECK: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x + 8 :: (store (p0) into @x)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x + 8
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
+ ; CHECK-NEXT: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x + 8 :: (store (p0) into @x)
%copy:gpr(p0) = COPY $x0
%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x + 8
%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x + 8
@@ -657,10 +663,11 @@ body: |
liveins: $x0
; CHECK-LABEL: name: store_adrp_add_low_unfoldable_offset
; CHECK: liveins: $x0
- ; CHECK: %copy:gpr64all = COPY $x0
- ; CHECK: %add_low:gpr64common = MOVaddr target-flags(aarch64-page) @x + 3, target-flags(aarch64-pageoff, aarch64-nc) @x + 3
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
- ; CHECK: STRXui [[COPY]], %add_low, 0 :: (store (p0) into @x)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: %add_low:gpr64common = MOVaddr target-flags(aarch64-page) @x + 3, target-flags(aarch64-pageoff, aarch64-nc) @x + 3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
+ ; CHECK-NEXT: STRXui [[COPY]], %add_low, 0 :: (store (p0) into @x)
%copy:gpr(p0) = COPY $x0
%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x + 3
%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x + 3
@@ -677,20 +684,20 @@ body: |
; CHECK-LABEL: name: truncstores
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: %val32:gpr32 = COPY $w1
- ; CHECK: %val64:gpr64 = COPY $x2
- ; CHECK: STRBBui %val32, [[COPY]], 0 :: (store (s8))
- ; CHECK: STRBBui %val32, [[COPY]], 43 :: (store (s8))
- ; CHECK: STRHHui %val32, [[COPY]], 0 :: (store (s16))
- ; CHECK: STURHHi %val32, [[COPY]], 43 :: (store (s16))
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store (s16))
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK: STURHHi [[COPY2]], [[COPY]], 43 :: (store (s16))
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK: STRWui [[COPY3]], [[COPY]], 0 :: (store (s32))
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY %val64.sub_32
- ; CHECK: STURWi [[COPY4]], [[COPY]], 43 :: (store (s32))
+ ; CHECK-NEXT: %val32:gpr32 = COPY $w1
+ ; CHECK-NEXT: %val64:gpr64 = COPY $x2
+ ; CHECK-NEXT: STRBBui %val32, [[COPY]], 0 :: (store (s8))
+ ; CHECK-NEXT: STRBBui %val32, [[COPY]], 43 :: (store (s8))
+ ; CHECK-NEXT: STRHHui %val32, [[COPY]], 0 :: (store (s16))
+ ; CHECK-NEXT: STURHHi %val32, [[COPY]], 43 :: (store (s16))
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY %val64.sub_32
+ ; CHECK-NEXT: STRHHui [[COPY1]], [[COPY]], 0 :: (store (s16))
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY %val64.sub_32
+ ; CHECK-NEXT: STURHHi [[COPY2]], [[COPY]], 43 :: (store (s16))
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY %val64.sub_32
+ ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 0 :: (store (s32))
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY %val64.sub_32
+ ; CHECK-NEXT: STURWi [[COPY4]], [[COPY]], 43 :: (store (s32))
%0:gpr(p0) = COPY $x0
%val32:gpr(s32) = COPY $w1
%val64:gpr(s64) = COPY $x2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
index 1b82d965d8c43..f67e432514d38 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -26,8 +26,8 @@ body: |
; CHECK-LABEL: name: trunc_s32_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(s64) = COPY $x0
%1(s32) = G_TRUNC %0
$w0 = COPY %1(s32)
@@ -48,9 +48,9 @@ body: |
; CHECK-LABEL: name: trunc_s8_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
- ; CHECK: $w0 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY2]]
%0(s64) = COPY $x0
%1(s8) = G_TRUNC %0
%2:gpr(s32) = G_ANYEXT %1
@@ -72,8 +72,8 @@ body: |
; CHECK-LABEL: name: trunc_s1_s32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(s32) = COPY $w0
%1(s1) = G_TRUNC %0
%2:gpr(s32) = G_ANYEXT %1
@@ -94,8 +94,8 @@ body: |
; CHECK-LABEL: name: trunc_s64_s128
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
- ; CHECK: $x0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
+ ; CHECK-NEXT: $x0 = COPY [[COPY1]]
%0(s128) = COPY $q0
%1(s64) = G_TRUNC %0
$x0 = COPY %1(s64)
@@ -115,8 +115,8 @@ body: |
; CHECK-LABEL: name: trunc_s32_s128
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
- ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
%0(s128) = COPY $q0
%1(s32) = G_TRUNC %0
$w0 = COPY %1(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
index 33252e6e62e58..3ea96401c2409 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
@@ -14,14 +14,15 @@ body: |
; CHECK-LABEL: name: uaddo_s32
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%3:gpr(s32), %4:gpr(s1) = G_UADDO %0, %1
@@ -43,14 +44,15 @@ body: |
; CHECK-LABEL: name: uaddo_s64
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%3:gpr(s64), %4:gpr(s1) = G_UADDO %0, %1
@@ -73,11 +75,12 @@ body: |
;
; CHECK-LABEL: name: uaddo_s32_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 16
%add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy, %constant
@@ -98,12 +101,13 @@ body: |
;
; CHECK-LABEL: name: uaddo_s32_shifted
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy1:gpr32 = COPY $w0
- ; CHECK: %copy2:gpr32 = COPY $w1
- ; CHECK: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %copy2:gpr32 = COPY $w1
+ ; CHECK-NEXT: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy1:gpr(s32) = COPY $w0
%copy2:gpr(s32) = COPY $w1
%constant:gpr(s32) = G_CONSTANT i32 16
@@ -126,11 +130,12 @@ body: |
;
; CHECK-LABEL: name: uaddo_s32_neg_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 -16
%add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy, %constant
@@ -150,12 +155,13 @@ body: |
; Check that we get ADDSXrx.
; CHECK-LABEL: name: uaddo_arith_extended
; CHECK: liveins: $w0, $x0
- ; CHECK: %reg0:gpr64sp = COPY $x0
- ; CHECK: %reg1:gpr32 = COPY $w0
- ; CHECK: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
- ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
- ; CHECK: $x0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
+ ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%reg1:gpr(s32) = COPY $w0
%ext:gpr(s64) = G_ZEXT %reg1(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
index 2a23ffe816f67..b99a524b48ec6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
@@ -14,14 +14,15 @@ body: |
; CHECK-LABEL: name: usubo_s32
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%3:gpr(s32), %4:gpr(s1) = G_USUBO %0, %1
@@ -43,14 +44,15 @@ body: |
; CHECK-LABEL: name: usubo_s64
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
- ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
- ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
- ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
- ; CHECK: $w0 = COPY [[UBFMWri1]]
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
+ ; CHECK-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%3:gpr(s64), %4:gpr(s1) = G_USUBO %0, %1
@@ -73,11 +75,12 @@ body: |
;
; CHECK-LABEL: name: usubo_s32_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 16
%add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
@@ -98,12 +101,13 @@ body: |
;
; CHECK-LABEL: name: usubo_s32_shifted
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy1:gpr32 = COPY $w0
- ; CHECK: %copy2:gpr32 = COPY $w1
- ; CHECK: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %copy2:gpr32 = COPY $w1
+ ; CHECK-NEXT: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy1:gpr(s32) = COPY $w0
%copy2:gpr(s32) = COPY $w1
%constant:gpr(s32) = G_CONSTANT i32 16
@@ -126,11 +130,12 @@ body: |
;
; CHECK-LABEL: name: usubo_s32_neg_imm
; CHECK: liveins: $w0, $w1, $x2
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
- ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
- ; CHECK: $w0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
+ ; CHECK-NEXT: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK-NEXT: $w0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:gpr(s32) = COPY $w0
%constant:gpr(s32) = G_CONSTANT i32 -16
%add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
@@ -150,12 +155,13 @@ body: |
; Check that we get ADDSXrx.
; CHECK-LABEL: name: usubo_arith_extended
; CHECK: liveins: $w0, $x0
- ; CHECK: %reg0:gpr64sp = COPY $x0
- ; CHECK: %reg1:gpr32 = COPY $w0
- ; CHECK: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
- ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
- ; CHECK: $x0 = COPY %add
- ; CHECK: RET_ReallyLR implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
+ ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
+ ; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
+ ; CHECK-NEXT: %flags:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
+ ; CHECK-NEXT: $x0 = COPY %add
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
%reg0:gpr(s64) = COPY $x0
%reg1:gpr(s32) = COPY $w0
%ext:gpr(s64) = G_ZEXT %reg1(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
index 60af59672a4ca..1e15322f41f80 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
@@ -21,11 +21,11 @@ body: |
; CHECK-LABEL: name: zext_of_load_copy
; CHECK: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
- ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
- ; CHECK: $x0 = COPY [[ANDXri]]
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
+ ; CHECK-NEXT: $x0 = COPY [[ANDXri]]
%3:gpr(p0) = G_IMPLICIT_DEF
%2:gpr(s8) = G_LOAD %3(p0) :: (load (s8))
%4:gpr(s64) = G_ZEXT %2(s8)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
index d8f962cdfb76f..7d45abd8152cc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
@@ -15,12 +15,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: tbnzx_slt
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: TBNZX %copy, 63, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: TBNZX %copy, 63, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -42,12 +44,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: tbnzw_slt
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: TBNZW %copy, 31, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBNZW %copy, 31, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -69,13 +73,15 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: no_tbnz_not_zero
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -97,13 +103,15 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_and
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -128,14 +136,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_commute
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: %zero:gpr64 = COPY $xzr
- ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %zero, %copy, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: %zero:gpr64 = COPY $xzr
+ ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %zero, %copy, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
index 2ac3d567ed80f..07c1aaa345336 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
@@ -15,12 +15,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: tbzx_sgt
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: TBZX %copy, 63, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: TBZX %copy, 63, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -42,12 +44,14 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: tbzw_sgt
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32 = COPY $w0
- ; CHECK: TBZW %copy, 31, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: TBZW %copy, 31, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -69,13 +73,15 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: no_tbz_not_negative_one
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr32sp = COPY $w0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 12, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -97,14 +103,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_fold_and
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: %and:gpr64sp = ANDXri %copy, 8000
- ; CHECK: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %and, 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 12, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: %and:gpr64sp = ANDXri %copy, 8000
+ ; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %and, 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
@@ -129,14 +137,16 @@ regBankSelected: true
body: |
; CHECK-LABEL: name: dont_commute
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %copy:gpr64 = COPY $x0
- ; CHECK: %negative_one:gpr64 = MOVi64imm -1
- ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %negative_one, %copy, implicit-def $nzcv
- ; CHECK: Bcc 12, %bb.1, implicit $nzcv
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
+ ; CHECK-NEXT: %negative_one:gpr64 = MOVi64imm -1
+ ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %negative_one, %copy, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 12, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
index dcd80c403e451..a8ff48599bb03 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
@@ -22,12 +22,14 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: s1_no_copy
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %narrow:gpr32 = IMPLICIT_DEF
- ; CHECK: TBNZW %narrow, 0, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %narrow:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: TBNZW %narrow, 0, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
%narrow:gpr(s1) = G_IMPLICIT_DEF
@@ -47,12 +49,14 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: s16_no_copy
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %narrow:gpr32 = IMPLICIT_DEF
- ; CHECK: TBNZW %narrow, 0, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %narrow:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: TBNZW %narrow, 0, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
%narrow:gpr(s16) = G_IMPLICIT_DEF
@@ -74,13 +78,15 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: p0_no_copy
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %glob:gpr64common = MOVaddr target-flags(aarch64-page) @glob, target-flags(aarch64-pageoff, aarch64-nc) @glob
- ; CHECK: %load:gpr32 = LDRBBui %glob, 0 :: (dereferenceable load (s8) from @glob, align 4)
- ; CHECK: TBNZW %load, 0, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %glob:gpr64common = MOVaddr target-flags(aarch64-page) @glob, target-flags(aarch64-pageoff, aarch64-nc) @glob
+ ; CHECK-NEXT: %load:gpr32 = LDRBBui %glob, 0 :: (dereferenceable load (s8) from @glob, align 4)
+ ; CHECK-NEXT: TBNZW %load, 0, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
%glob:gpr(p0) = G_GLOBAL_VALUE @glob
@@ -103,15 +109,17 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: widen_s32_to_s64
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $w0
- ; CHECK: %reg:gpr32all = COPY $w0
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, %reg, %subreg.sub_32
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
- ; CHECK: TBZX [[COPY]], 33, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg:gpr32all = COPY $w0
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, %reg, %subreg.sub_32
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: TBZX [[COPY]], 33, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $w0
@@ -139,14 +147,16 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: widen_s16_to_s64
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: %reg:gpr32 = IMPLICIT_DEF
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, %reg, %subreg.sub_32
- ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
- ; CHECK: TBZX [[COPY]], 33, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %reg:gpr32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, %reg, %subreg.sub_32
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: TBZX [[COPY]], 33, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
%reg:gpr(s16) = G_IMPLICIT_DEF
@@ -174,15 +184,17 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: narrow_s64_to_s32
; CHECK: bb.0:
- ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
- ; CHECK: liveins: $x0
- ; CHECK: %wide:gpr64all = COPY $x0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %wide.sub_32
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: TBNZW [[COPY1]], 0, %bb.1
- ; CHECK: B %bb.0
- ; CHECK: bb.1:
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %wide:gpr64all = COPY $x0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %wide.sub_32
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.1
+ ; CHECK-NEXT: B %bb.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: RET_ReallyLR
bb.0:
successors: %bb.0, %bb.1
liveins: $x0
diff --git a/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir b/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
index ec9c11ae1ccd0..ad677d1dc2225 100644
--- a/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
@@ -1,13 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
---- |
-
- define void @atomic_memoperands() {
- ret void
- }
-
-...
---
name: atomic_memoperands
body: |
@@ -15,13 +8,13 @@ body: |
; CHECK-LABEL: name: atomic_memoperands
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load unordered (s64))
- ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic (s32))
- ; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire (s16))
- ; CHECK: G_STORE [[LOAD2]](s16), [[COPY]](p0) :: (store release (s16))
- ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel (s32))
- ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst (s64))
- ; CHECK: RET_ReallyLR
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load unordered (s64))
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic (s32))
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire (s16))
+ ; CHECK-NEXT: G_STORE [[LOAD2]](s16), [[COPY]](p0) :: (store release (s16))
+ ; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel (s32))
+ ; CHECK-NEXT: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst (s64))
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s64) = G_LOAD %0(p0) :: (load unordered (s64))
%2:_(s32) = G_LOAD %0(p0) :: (load monotonic (s32))
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