[llvm] 7619218 - [RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 11 10:15:16 PDT 2022
Author: Craig Topper
Date: 2022-04-11T10:14:48-07:00
New Revision: 76192182d0ca8e0c82c6d7aa9c11de07328b4c62
URL: https://github.com/llvm/llvm-project/commit/76192182d0ca8e0c82c6d7aa9c11de07328b4c62
DIFF: https://github.com/llvm/llvm-project/commit/76192182d0ca8e0c82c6d7aa9c11de07328b4c62.diff
LOG: [RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option.
This was added before Zve extensions were defined. I think users
should use Zve32x or Zve32f now. Though we will lose support for limiting
ELEN to 16 or 8, but I hope no one was using that.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D123418
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7b5f3b7eb1ac4..be54958c4934d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1621,7 +1621,7 @@ static bool useRVVForFixedLengthVectorVT(MVT VT,
}
// Reject elements larger than ELEN.
- if (EltVT.getSizeInBits() > Subtarget.getMaxELENForFixedLengthVectors())
+ if (EltVT.getSizeInBits() > Subtarget.getELEN())
return false;
unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen);
@@ -1650,7 +1650,7 @@ static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT,
"Expected legal fixed length vector!");
unsigned MinVLen = Subtarget.getMinRVVVectorSizeInBits();
- unsigned MaxELen = Subtarget.getMaxELENForFixedLengthVectors();
+ unsigned MaxELen = Subtarget.getELEN();
MVT EltVT = VT.getVectorElementType();
switch (EltVT.SimpleTy) {
@@ -2050,8 +2050,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
// codegen across RV32 and RV64.
unsigned NumViaIntegerBits =
std::min(std::max(NumElts, 8u), Subtarget.getXLen());
- NumViaIntegerBits = std::min(NumViaIntegerBits,
- Subtarget.getMaxELENForFixedLengthVectors());
+ NumViaIntegerBits = std::min(NumViaIntegerBits, Subtarget.getELEN());
if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
// If we have to use more than one INSERT_VECTOR_ELT then this
// optimization is likely to increase code size; avoid peforming it in
@@ -2435,7 +2434,7 @@ static SDValue lowerScalarSplat(SDValue Passthru, SDValue Scalar, SDValue VL,
static bool isInterleaveShuffle(ArrayRef<int> Mask, MVT VT, bool &SwapSources,
const RISCVSubtarget &Subtarget) {
// We need to be able to widen elements to the next larger integer type.
- if (VT.getScalarSizeInBits() >= Subtarget.getMaxELENForFixedLengthVectors())
+ if (VT.getScalarSizeInBits() >= Subtarget.getELEN())
return false;
int Size = Mask.size();
@@ -4516,7 +4515,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
unsigned WidenVecLen;
SDValue ExtractElementIdx;
SDValue ExtractBitIdx;
- unsigned MaxEEW = Subtarget.getMaxELENForFixedLengthVectors();
+ unsigned MaxEEW = Subtarget.getELEN();
MVT LargestEltVT = MVT::getIntegerVT(
std::min(MaxEEW, unsigned(XLenVT.getSizeInBits())));
if (NumElts <= LargestEltVT.getSizeInBits()) {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3aa69e851df33..185845f55cb31 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -46,11 +46,6 @@ static cl::opt<unsigned> RVVVectorLMULMax(
"Fractional LMUL values are not supported."),
cl::init(8), cl::Hidden);
-static cl::opt<unsigned> RVVVectorELENMax(
- "riscv-v-fixed-length-vector-elen-max",
- cl::desc("The maximum ELEN value to use for fixed length vectors."),
- cl::init(64), cl::Hidden);
-
static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
"riscv-disable-using-constant-pool-for-large-ints",
cl::desc("Disable using constant pool for large integers."),
@@ -192,17 +187,6 @@ unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
}
-unsigned RISCVSubtarget::getMaxELENForFixedLengthVectors() const {
- assert(hasVInstructions() &&
- "Tried to get maximum ELEN without Zve or V extension support!");
- assert(RVVVectorELENMax <= 64 && RVVVectorELENMax >= 8 &&
- isPowerOf2_32(RVVVectorELENMax) &&
- "V extension requires a ELEN to be a power of 2 between 8 and 64!");
- unsigned ELEN = hasVInstructionsI64() ? 64 : 32;
- return PowerOf2Floor(
- std::max<unsigned>(std::min<unsigned>(RVVVectorELENMax, ELEN), 8));
-}
-
bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 038dd2b1876af..b71a032bfd7f6 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -191,6 +191,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
return 0;
}
+ unsigned getELEN() const {
+ assert(hasVInstructions() && "Expected V extension");
+ return hasVInstructionsI64() ? 64 : 32;
+ }
unsigned getMinVLen() const { return ZvlLen; }
unsigned getMaxVLen() const { return 65536; }
unsigned getRealMinVLen() const {
@@ -246,7 +250,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getMaxRVVVectorSizeInBits() const;
unsigned getMinRVVVectorSizeInBits() const;
unsigned getMaxLMULForFixedLengthVectors() const;
- unsigned getMaxELENForFixedLengthVectors() const;
bool useRVVForFixedLengthVectors() const;
};
} // End llvm namespace
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 5fdcbe6dd9158..951635c6d5717 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -247,8 +247,8 @@ InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
// Skip if element size of Dst or Src is bigger than ELEN.
- if (Src->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors() ||
- Dst->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
+ if (Src->getScalarSizeInBits() > ST->getELEN() ||
+ Dst->getScalarSizeInBits() > ST->getELEN())
return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
int ISD = TLI->InstructionOpcodeToISD(Opcode);
@@ -295,7 +295,7 @@ RISCVTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
// Skip if scalar size of Ty is bigger than ELEN.
- if (Ty->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
+ if (Ty->getScalarSizeInBits() > ST->getELEN())
return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
// IR Reduction is composed by two vmv and one rvv reduction instruction.
@@ -321,7 +321,7 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *VTy,
return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
// Skip if scalar size of VTy is bigger than ELEN.
- if (VTy->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
+ if (VTy->getScalarSizeInBits() > ST->getELEN())
return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
int ISD = TLI->InstructionOpcodeToISD(Opcode);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index bcc3182ea7808..60622bfc5ffdc 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -116,7 +116,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
// Don't allow elements larger than the ELEN.
// FIXME: How to limit for scalable vectors?
if (isa<FixedVectorType>(DataType) &&
- DataType->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
+ DataType->getScalarSizeInBits() > ST->getELEN())
return false;
if (Alignment <
@@ -144,7 +144,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
// Don't allow elements larger than the ELEN.
// FIXME: How to limit for scalable vectors?
if (isa<FixedVectorType>(DataType) &&
- DataType->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
+ DataType->getScalarSizeInBits() > ST->getELEN())
return false;
if (Alignment <
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
index 2755675f94c35..0753c479e2ef2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
@@ -5,13 +5,11 @@
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
; RUN: -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
-; RUN: -riscv-v-vector-bits-min=128 \
-; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zve32f,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
+; RUN: -riscv-v-vector-bits-min=128 -target-abi=ilp32d < %s \
; RUN: | FileCheck %s --check-prefixes=ELEN32,RV32ELEN32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
-; RUN: -riscv-v-vector-bits-min=128 \
-; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=lp64d < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zve32f,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
+; RUN: -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \
; RUN: | FileCheck %s --check-prefixes=ELEN32,RV64ELEN32
define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
index 99f64e73af2cc..7e38233b64952 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
@@ -1,11 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+d,+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+d,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; Test that limiting ELEN, either through the command line or zve32, scalarizes
-; elements larger than that and disables some fractional LMULs.
+; Test that limiting ELEN through zve32 scalarizes elements larger than 32 bits
+; and disables some fractional LMULs.
; This should use LMUL=1.
define void @add_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
index 875eff21ea7b6..275f31fb49ae2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -8,12 +8,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8
; Test with ELEN limited
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN32
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN32
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN16
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN16
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN8
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN8
+; RUN: llc -mtriple=riscv32 -mattr=+f,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+zve32f -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN32
define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) {
; CHECK-LABEL: buildvec_mask_nonconst_v1i1:
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